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pci_mmio_cfg: Always use pci_s_* functions

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When MMIO functions are available, the pci_s_* functions do exactly
the same thing. Drop the redundant pci_mmio_* versions.

Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Nico Huber
2021-10-14 18:16:39 +02:00
committed by Nico Huber
parent e01e25d4fc
commit f4f365fdd0
7 changed files with 30 additions and 65 deletions
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6
src/soc/intel/xeon_sp/bootblock.c
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@@ -56,9 +56,9 @@ void bootblock_soc_early_init(void)
pch_enable_lpc();
/* Set up P2SB BAR. This is needed for PCR to work */
uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
pci_mmio_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
}
void bootblock_soc_init(void)