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skylake: remove ec_smi_gpio and alt_gp_smi_en

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The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.

Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.

Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().

BUG=chrome-os-partner:43778
BRANCH=None
TEST=None

Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
2015-08-07 22:57:42 -05:00
parent 9a8dc37cdd
commit f50b25d7e2
8 changed files with 2 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/skylake/gpio.c
View File

@ -371,21 +371,3 @@ void gpio_enable_all_smi(void)
0xFFFFFFFF);
}
}
void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask)
{
u32 gpioindex = 0;
u32 smien = 0;
if (gpio_num > MAX_GPIO_NUMBER)
return;
gpioindex = (gpio_num / MAX_GPIO_PIN_PER_GROUP);
pcr_read32(gpio_group_info[gpioindex].community,
gpio_group_info[gpioindex].smienoffset, &smien);
smien |= mask;
/* Set all GPI SMI Enable bits by writing '1' */
pcr_write32(gpio_group_info[gpioindex].community,
gpio_group_info[gpioindex].smienoffset, smien);
}