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soc/intel/skylake: Limit xDCI feature when VBOOT is enabled

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Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.

This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.

Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie
2018-03-26 02:24:18 -07:00
parent 8b76605a4a
commit f5116952bb
15 changed files with 16 additions and 15 deletions
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8
src/soc/intel/skylake/chip_fsp20.c
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@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@@ -221,7 +222,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchHdaEnable = config->EnableAzalia;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;
params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
@@ -284,6 +284,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
/*
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