sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: remove LIDS field from global NVS

Browse Source 
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Stoneyridge SoC, remove it form the global
NVS and add an ACPI object for this in the DSDT of the mainboards that
use it in their ACPI code. Eventually the LIDS object should probably be
moved to the EC's ACPI code, but that's out of scope for this patch.

TEST=google/liara doesn't show ACPI errors in Linux' dmesg

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Felix Held
2023-01-20 21:08:08 +01:00
parent 584d5e1cba
commit f56b645f1f
3 changed files with 15 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/kahlee/dsdt.asl
View File

@ -16,6 +16,8 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl> #include <acpi/dsdt_top.asl>
#include <globalnvs.asl> #include <globalnvs.asl>
Name(LIDS, 0)
/* Globals for the platform */ /* Globals for the platform */
#include <variant/acpi/mainboard.asl> #include <variant/acpi/mainboard.asl>

13
src/soc/amd/stoneyridge/acpi/globalnvs.asl
View File

@ -9,13 +9,12 @@
Field (GNVS, ByteAcc, NoLock, Preserve) Field (GNVS, ByteAcc, NoLock, Preserve)
{ {
/* Miscellaneous */ /* Miscellaneous */
LIDS, 8, // 0x00 - LID State CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console
CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index
PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index GPEI, 64, // 0x0c - 0x13 - GPE Wake Source
GPEI, 64, // 0x0d - 0x14 - GPE Wake Source TMPS, 8, // 0x14 - Temperature Sensor ID
TMPS, 8, // 0x15 - Temperature Sensor ID TCRT, 8, // 0x15 - Critical Threshold
TCRT, 8, // 0x16 - Critical Threshold TPSV, 8, // 0x16 - Passive Threshold
TPSV, 8, // 0x17 - Passive Threshold
Offset (0x20), // 0x20 - AOAC Device Enables Offset (0x20), // 0x20 - AOAC Device Enables
, 5, , 5,
IC0E, 1, // I2C0, 5 IC0E, 1, // I2C0, 5

15
src/soc/amd/stoneyridge/include/soc/nvs.h
View File

@ -14,14 +14,13 @@
struct __packed global_nvs { struct __packed global_nvs {
/* Miscellaneous */ /* Miscellaneous */
uint8_t lids; /* 0x00 - LID State */ uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */ uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */ uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */
uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */ uint8_t tmps; /* 0x14 - Temperature Sensor ID */
uint8_t tmps; /* 0x15 - Temperature Sensor ID */ uint8_t tcrt; /* 0x15 - Critical Threshold */
uint8_t tcrt; /* 0x16 - Critical Threshold */ uint8_t tpsv; /* 0x16 - Passive Threshold */
uint8_t tpsv; /* 0x17 - Passive Threshold */ uint8_t pad1[9];
uint8_t pad1[8];
aoac_devs_t aoac; /* 0x20 - AOAC device enables */ aoac_devs_t aoac; /* 0x20 - AOAC device enables */
uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */ uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */
uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */ uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */