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addw3, bonw15: disable AER on TBT root port

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Change-Id: I23301f432c590dfe16bec1a90f2dee227ebf84f9
This commit is contained in:
Jeremy Soller
2023-03-31 12:56:30 -06:00
parent a739c5311c
commit f5ac4c08d3
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/system76/rpl/variants/addw3/overridetree.cb
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@@ -149,7 +149,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(21)]" = "{ register "pch_pcie_rp[PCH_RP(21)]" = "{
.clk_src = 15, .clk_src = 15,
.clk_req = 15, .clk_req = 15,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
}" }"
chip drivers/usb/acpi chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB" register "type" = "UPC_TYPE_HUB"

2
src/mainboard/system76/rpl/variants/bonw15/overridetree.cb
View File

@@ -89,7 +89,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(9)]" = "{ register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 15, .clk_src = 15,
.clk_req = 15, .clk_req = 15,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
}" }"
end end