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sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN

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According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.

Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui
2024-04-15 23:14:56 -04:00
committed by Felix Held
parent 8b5aacca3f
commit f5b993de4f
1 changed files with 1 additions and 1 deletions
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2
src/superio/nuvoton/nct6779d/nct6779d.h
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@@ -22,7 +22,7 @@
/* virtual LDN for GPIO */ /* virtual LDN for GPIO */
#define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V) #define NCT6779D_GPIOBASE ((3 << 8) | NCT6779D_WDT1_GPIO01_V)
#define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V) #define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V)
#define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V) #define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V)