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driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibility

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Included <efi/efi_datatype.h> to address coreboot style header
definitions rather using EDK2 header <Base.h>.

TEST=Able to build google/rex0.

Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-05-09 11:21:57 +00:00
parent 3a3804f458
commit f5be5e4999
1 changed files with 2 additions and 1 deletions
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src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
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@@ -7,6 +7,8 @@
#pragma pack(push) #pragma pack(push)
#include <efi/efi_datatype.h>
/** /**
* These includes are required to include headers that are missing in * These includes are required to include headers that are missing in
* the FSP headers. Import order matter for the correct PiHob definition * the FSP headers. Import order matter for the correct PiHob definition
@@ -24,7 +26,6 @@
* This file is a implementation specific header. i.e. different * This file is a implementation specific header. i.e. different
* FSP implementations for different chipsets. * FSP implementations for different chipsets.
*/ */
#include <Base.h>
#include <FspmUpd.h> #include <FspmUpd.h>
#include <FspsUpd.h> #include <FspsUpd.h>
#if CONFIG(MRC_CACHE_USING_MRC_VERSION) #if CONFIG(MRC_CACHE_USING_MRC_VERSION)