intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@@ -26,3 +26,7 @@ config CPU_INTEL_COMMON_HYPERTHREADING
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bool
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endif
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config CPU_INTEL_COMMON_SMM
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bool
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default y if CPU_INTEL_COMMON
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@@ -45,49 +45,7 @@
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#define SMRR_SUPPORTED (1 << 11)
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#define PRMRR_SUPPORTED (1 << 12)
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struct smm_relocation_params {
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uintptr_t ied_base;
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size_t ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t prmrr_base;
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msr_t prmrr_mask;
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msr_t uncore_prmrr_base;
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msr_t uncore_prmrr_mask;
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/* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE */
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int smm_save_state_in_msrs;
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};
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static inline void write_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
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wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
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wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
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}
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static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG,
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"Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->uncore_prmrr_base.lo,
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relo_params->uncore_prmrr_mask.lo);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
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wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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1
src/cpu/intel/smm/Makefile.inc
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1
src/cpu/intel/smm/Makefile.inc
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@@ -0,0 +1 @@
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c
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@@ -39,17 +39,6 @@
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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struct smm_relocation_params {
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uintptr_t ied_base;
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size_t ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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};
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
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differently. The MSR are at different location from the rest
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and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
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@@ -88,15 +77,6 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
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wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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uintptr_t tseg_base;
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16
src/cpu/intel/smm/smm_reloc.c
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16
src/cpu/intel/smm/smm_reloc.c
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@@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/intel/smm_reloc.h>
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struct smm_relocation_params smm_reloc_params;
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