intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@@ -41,7 +41,6 @@
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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#include <timer.h>
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@@ -1,40 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_SMM_H_
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#define _SOC_SMM_H_
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include <intelblocks/smihandler.h>
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#include <soc/gpio.h>
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struct smm_relocation_params {
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uintptr_t ied_base;
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size_t ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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/*
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* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE
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*/
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int smm_save_state_in_msrs;
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};
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#endif
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@@ -31,20 +31,9 @@
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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