cpu: Add initial support for Allwinner A10 SoC
Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4549 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Alexandru Gagniuc
137
src/cpu/allwinner/a10/clock.h
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137
src/cpu/allwinner/a10/clock.h
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/*
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* Definitions for clock control and gating on Allwinner CPUs
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*
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* Copyright (C) 2007-2011 Allwinner Technology Co., Ltd.
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* Tom Cubie <tangliang@allwinnertech.com>
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* Subject to the GNU GPL v2, or (at your option) any later version.
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*/
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#ifndef CPU_ALLWINNER_A10_CLOCK_H
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#define CPU_ALLWINNER_A10_CLOCK_H
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#include "memmap.h"
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#include <types.h>
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/* CPU_AHB_APB0 config values */
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#define CPU_CLK_SRC_MASK (3 << 16)
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#define CPU_CLK_SRC_OSC24M (1 << 16)
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#define CPU_CLK_SRC_PLL1 (2 << 16)
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#define APB0_DIV_MASK (3 << 8)
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#define APB0_DIV_1 (0 << 8)
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#define APB0_DIV_2 (1 << 8)
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#define APB0_DIV_4 (2 << 8)
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#define APB0_DIV_8 (3 << 8)
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#define AHB_DIV_MASK (3 << 4)
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#define AHB_DIV_1 (0 << 4)
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#define AHB_DIV_2 (1 << 4)
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#define AHB_DIV_4 (2 << 4)
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#define AHB_DIV_8 (3 << 4)
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#define AXI_DIV_MASK (3 << 0)
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#define AXI_DIV_1 (0 << 0)
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#define AXI_DIV_2 (1 << 0)
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#define AXI_DIV_3 (2 << 0)
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#define AXI_DIV_4 (3 << 0)
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/* APB1_CLK_DIV values */
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#define APB1_CLK_SRC_MASK (3 << 24)
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#define APB1_CLK_SRC_OSC24M (0 << 24)
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#define APB1_CLK_SRC_PLL6 (1 << 24)
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#define APB1_CLK_SRC_32K (2 << 24)
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#define APB1_RAT_N_MASK (3 << 16)
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#define APB1_RAT_N(m) (((m) & 0x3) << 16)
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#define APB1_RAT_M_MASK 0x1f << 0)
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#define APB1_RAT_M(n) (((n) & 0x1f) << 0)
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/* APB0_GATING values */
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#define APB0_GATE_KEYPAD (1 << 10)
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#define APB0_GATE_IR(x) (((1 << (x)) & 0x3) << 6)
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#define APB0_GATE_PIO (1 << 5)
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#define APB0_GATE_IIS (1 << 3)
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#define APB0_GATE_AC97 (1 << 2)
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#define APB0_GATE_CODEC (1 << 0)
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/* APB1_GATING values */
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#define APB1_GATE_UART(x) (((1 << (x)) & 0xff) << 16)
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#define APB1_GATE_PS2(x) (((1 << (x)) & 0x3) << 6)
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#define APB1_GATE_CAN (1 << 4)
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#define APB1_GATE_TWI(x) (((1 << (x)) & 0x7) << 0)
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struct a10_ccm {
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u32 pll1_cfg; /* 0x00 pll1 control */
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u32 pll1_tun; /* 0x04 pll1 tuning */
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u32 pll2_cfg; /* 0x08 pll2 control */
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u32 pll2_tun; /* 0x0c pll2 tuning */
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u32 pll3_cfg; /* 0x10 pll3 control */
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u8 res0[0x4];
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u32 pll4_cfg; /* 0x18 pll4 control */
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u8 res1[0x4];
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u32 pll5_cfg; /* 0x20 pll5 control */
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u32 pll5_tun; /* 0x24 pll5 tuning */
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u32 pll6_cfg; /* 0x28 pll6 control */
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u32 pll6_tun; /* 0x2c pll6 tuning */
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u32 pll7_cfg; /* 0x30 pll7 control */
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u32 pll1_tun2; /* 0x34 pll5 tuning2 */
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u8 res2[0x4];
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u32 pll5_tun2; /* 0x3c pll5 tuning2 */
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u8 res3[0xc];
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u32 pll_lock_dbg; /* 0x4c pll lock time debug */
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u32 osc24m_cfg; /* 0x50 osc24m control */
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u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
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u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
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u32 axi_gate; /* 0x5c axi module clock gating */
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u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
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u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
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u32 apb0_gate; /* 0x68 apb0 module clock gating */
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u32 apb1_gate; /* 0x6c apb1 module clock gating */
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u8 res4[0x10];
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u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
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u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
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u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
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u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
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u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
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u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
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u32 ts_clk_cfg; /* 0x98 transport stream clock control */
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u32 ss_clk_cfg; /* 0x9c */
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u32 spi0_clk_cfg; /* 0xa0 */
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u32 spi1_clk_cfg; /* 0xa4 */
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u32 spi2_clk_cfg; /* 0xa8 */
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u32 pata_clk_cfg; /* 0xac */
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u32 ir0_clk_cfg; /* 0xb0 */
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u32 ir1_clk_cfg; /* 0xb4 */
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u32 iis_clk_cfg; /* 0xb8 */
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u32 ac97_clk_cfg; /* 0xbc */
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u32 spdif_clk_cfg; /* 0xc0 */
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u32 keypad_clk_cfg; /* 0xc4 */
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u32 sata_clk_cfg; /* 0xc8 */
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u32 usb_clk_cfg; /* 0xcc */
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u32 gps_clk_cfg; /* 0xd0 */
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u32 spi3_clk_cfg; /* 0xd4 */
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u8 res5[0x28];
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u32 dram_clk_cfg; /* 0x100 */
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u32 be0_clk_cfg; /* 0x104 */
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u32 be1_clk_cfg; /* 0x108 */
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u32 fe0_clk_cfg; /* 0x10c */
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u32 fe1_clk_cfg; /* 0x110 */
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u32 mp_clk_cfg; /* 0x114 */
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u32 lcd0_ch0_clk_cfg; /* 0x118 */
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u32 lcd1_ch0_clk_cfg; /* 0x11c */
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u32 csi_isp_clk_cfg; /* 0x120 */
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u8 res6[0x4];
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u32 tvd_clk_reg; /* 0x128 */
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u32 lcd0_ch1_clk_cfg; /* 0x12c */
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u32 lcd1_ch1_clk_cfg; /* 0x130 */
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u32 csi0_clk_cfg; /* 0x134 */
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u32 csi1_clk_cfg; /* 0x138 */
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u32 ve_clk_cfg; /* 0x13c */
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u32 audio_codec_clk_cfg; /* 0x140 */
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u32 avs_clk_cfg; /* 0x144 */
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u32 ace_clk_cfg; /* 0x148 */
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u32 lvds_clk_cfg; /* 0x14c */
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u32 hdmi_clk_cfg; /* 0x150 */
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u32 mali_clk_cfg; /* 0x154 */
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u8 res7[0x4];
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u32 mbus_clk_cfg; /* 0x15c */
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} __attribute__ ((packed));
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#endif /* CPU_ALLWINNER_A10_CLOCK_H */
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