vendorcode/amd: Drop multiple copies of gcc-intrin.h
Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Stefan Reinauer
parent
069c11e8b3
commit
f652f82137
@ -255,7 +255,7 @@
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#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
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#define MAKE_AS_A_STRING(arg) #arg
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#include <stddef.h>
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#include "gcc-intrin.h"
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#include <gcc-intrin.h>
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#include <assert.h>
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#include <console/console.h>
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@ -18,7 +18,7 @@
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# AGESA V5 Files
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AGESA_ROOT = src/vendorcode/amd/agesa/f10
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AGESA_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
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AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
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AGESA_INC += -I$(AGESA_ROOT)
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AGESA_INC += -I$(AGESA_ROOT)/../common
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AGESA_INC += -I$(AGESA_ROOT)/Include
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@ -1,615 +0,0 @@
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/*
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* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
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* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#if defined (__GNUC__)
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#include <stdint.h>
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/* I/O intrin functions. */
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static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
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{
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uint8_t value;
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__asm__ __volatile__ (
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"in %1, %0"
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: "=a" (value)
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: "Nd" (Port)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
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{
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uint16_t value;
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__asm__ __volatile__ (
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"in %1, %0"
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: "=a" (value)
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: "Nd" (Port)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
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{
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uint32_t value;
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__asm__ __volatile__ (
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"in %1, %0"
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: "=a" (value)
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: "Nd" (Port)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
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{
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__asm__ __volatile__ (
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"out %0, %1"
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:
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: "a" (Data), "Nd" (Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
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{
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__asm__ __volatile__ (
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"out %0, %1"
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:
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: "a" (Data), "Nd" (Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
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{
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__asm__ __volatile__ (
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"out %0, %1"
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:
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: "a" (Data), "Nd" (Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; insb"
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: "+D" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; insw"
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: "+D" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; insl"
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: "+D" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; outsb"
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: "+S" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; outsw"
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: "+S" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
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{
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__asm__ __volatile__ (
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"rep ; outsl"
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: "+S" (Buffer), "+c" (Count)
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: "d"(Port)
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);
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%dr0, %[value]"
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: [value] "=r" (value)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%dr1, %[value]"
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: [value] "=r" (value)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%dr2, %[value]"
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: [value] "=r" (value)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%dr3, %[value]"
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: [value] "=r" (value)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%dr7, %[value]"
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: [value] "=r" (value)
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);
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
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{
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switch (reg){
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case 0:
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return __readdr0 ();
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break;
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case 1:
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return __readdr1 ();
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break;
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case 2:
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return __readdr2 ();
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break;
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case 3:
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return __readdr3 ();
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break;
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case 7:
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return __readdr7 ();
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break;
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default:
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return -1;
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}
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}
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static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%dr0"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%dr1"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%dr2"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%dr3"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%dr7"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
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{
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switch (reg){
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case 0:
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__writedr0 (Data);
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break;
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case 1:
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__writedr1 (Data);
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break;
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case 2:
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__writedr2 (Data);
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break;
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case 3:
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__writedr3 (Data);
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break;
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case 7:
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__writedr7 (Data);
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break;
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default:
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;
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}
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr0, %[value]"
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: [value] "=r" (value));
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr2, %[value]"
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: [value] "=r" (value));
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr3, %[value]"
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: [value] "=r" (value));
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr4, %[value]"
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: [value] "=r" (value));
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
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{
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unsigned long value;
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__asm__ __volatile__ (
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"mov %%cr8, %[value]"
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: [value] "=r" (value));
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return value;
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}
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static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
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{
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switch (reg){
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case 0:
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return __readcr0 ();
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break;
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case 2:
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return __readcr2 ();
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break;
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case 3:
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return __readcr3 ();
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break;
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case 4:
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return __readcr4 ();
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break;
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case 8:
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return __readcr8 ();
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break;
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default:
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return -1;
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}
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}
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static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr0"
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:
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: "r" (Data)
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: "memory"
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);
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}
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static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr2"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr3"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr4"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
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{
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__asm__ __volatile__ (
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"mov %0, %%cr8"
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:
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: "r" (Data)
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);
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}
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static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
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{
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switch (reg){
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case 0:
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__writecr0 (Data);
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break;
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case 2:
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__writecr2 (Data);
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break;
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case 3:
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__writecr3 (Data);
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break;
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case 4:
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__writecr4 (Data);
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break;
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case 8:
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__writecr8 (Data);
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break;
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default:
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;
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}
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}
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static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
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{
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UINT64 retval;
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__asm__ __volatile__(
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"rdmsr"
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: "=A" (retval)
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: "c" (msr)
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);
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return retval;
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}
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static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
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{
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__asm__ __volatile__ (
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"wrmsr"
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:
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: "c" (msr), "A" (Value)
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);
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}
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static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
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{
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UINT64 retval;
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__asm__ __volatile__ (
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"rdtsc"
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: "=A" (retval));
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return retval;
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}
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static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
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{
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__asm__ __volatile__(
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"cpuid"
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:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
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: "a" (InfoType)
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);
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}
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|
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static __inline__ __attribute__((always_inline)) void _disable(void)
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{
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__asm__ __volatile__ ("cli");
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}
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static __inline__ __attribute__((always_inline)) void _enable(void)
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{
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__asm__ __volatile__ ("sti");
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}
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static __inline__ __attribute__((always_inline)) void __halt(void)
|
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{
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__asm__ __volatile__ ("hlt");
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}
|
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|
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static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
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{
|
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__asm__ __volatile__ ("int3");
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}
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static __inline__ __attribute__((always_inline)) void __invd(void)
|
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{
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__asm__ __volatile__ ("invd");
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}
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static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
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{
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__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -30,7 +30,7 @@
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f12
|
||||
|
||||
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/../common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -30,7 +30,7 @@
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f14
|
||||
|
||||
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/../common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Include
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -19,7 +19,7 @@
|
||||
AGESA_ROOT ?= $(PWD)
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f15
|
||||
|
||||
AGESA_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/../common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Include
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -30,7 +30,7 @@
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f15tn
|
||||
|
||||
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/../common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Include
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -30,7 +30,7 @@
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f16kb
|
||||
|
||||
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC = -I$(src)/vendorcode/amd/include -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/../common
|
||||
AGESA_INC += -I$(AGESA_ROOT)/Include
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -255,7 +255,7 @@
|
||||
#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
|
||||
#define MAKE_AS_A_STRING(arg) #arg
|
||||
#include <stddef.h>
|
||||
#include "gcc-intrin.h"
|
||||
#include <gcc-intrin.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -255,7 +255,7 @@
|
||||
#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
|
||||
#define MAKE_AS_A_STRING(arg) #arg
|
||||
#include <stddef.h>
|
||||
#include "gcc-intrin.h"
|
||||
#include <gcc-intrin.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -275,7 +275,7 @@
|
||||
#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
|
||||
#define MAKE_AS_A_STRING(arg) #arg
|
||||
#include <stddef.h>
|
||||
#include "gcc-intrin.h"
|
||||
#include <gcc-intrin.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
|
||||
@ -1,615 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved.
|
||||
* Copyright (c) 2014, Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#include <stdint.h>
|
||||
/* I/O intrin functions. */
|
||||
static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
|
||||
{
|
||||
uint16_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"in %1, %0"
|
||||
: "=a" (value)
|
||||
: "Nd" (Port)
|
||||
);
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"out %0, %1"
|
||||
:
|
||||
: "a" (Data), "Nd" (Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insb"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insw"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; insl"
|
||||
: "+D" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsb"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsw"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"rep ; outsl"
|
||||
: "+S" (Buffer), "+c" (Count)
|
||||
: "d"(Port)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr0, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr1, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr2, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr3, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%dr7, %[value]"
|
||||
: [value] "=r" (value)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readdr0 ();
|
||||
break;
|
||||
|
||||
case 1:
|
||||
return __readdr1 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readdr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readdr3 ();
|
||||
break;
|
||||
|
||||
case 7:
|
||||
return __readdr7 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr1"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%dr7"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writedr0 (Data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
__writedr1 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writedr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writedr3 (Data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
__writedr7 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr0, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr2, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr3, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr4, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ __volatile__ (
|
||||
"mov %%cr8, %[value]"
|
||||
: [value] "=r" (value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
return __readcr0 ();
|
||||
break;
|
||||
|
||||
case 2:
|
||||
return __readcr2 ();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
return __readcr3 ();
|
||||
break;
|
||||
|
||||
case 4:
|
||||
return __readcr4 ();
|
||||
break;
|
||||
|
||||
case 8:
|
||||
return __readcr8 ();
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr0"
|
||||
:
|
||||
: "r" (Data)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr2"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr3"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr4"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mov %0, %%cr8"
|
||||
:
|
||||
: "r" (Data)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
|
||||
{
|
||||
switch (reg){
|
||||
case 0:
|
||||
__writecr0 (Data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
__writecr2 (Data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
__writecr3 (Data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
__writecr4 (Data);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
__writecr8 (Data);
|
||||
break;
|
||||
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
: "=A" (retval)
|
||||
: "c" (msr)
|
||||
);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
:
|
||||
: "c" (msr), "A" (Value)
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
|
||||
{
|
||||
UINT64 retval;
|
||||
__asm__ __volatile__ (
|
||||
"rdtsc"
|
||||
: "=A" (retval));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"cpuid"
|
||||
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
|
||||
: "a" (InfoType)
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _disable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("cli");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _enable(void)
|
||||
{
|
||||
__asm__ __volatile__ ("sti");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __halt(void)
|
||||
{
|
||||
__asm__ __volatile__ ("hlt");
|
||||
}
|
||||
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
|
||||
{
|
||||
__asm__ __volatile__ ("int3");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __invd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("invd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
|
||||
{
|
||||
__asm__ __volatile__ ("wbinvd");
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
|
||||
{
|
||||
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsbyte(const unsigned long Offset, const uint8_t Data)
|
||||
{
|
||||
__asm__ ("movb %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "iq" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsword(const unsigned long Offset, const uint16_t Data)
|
||||
{
|
||||
__asm__ ("movw %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void
|
||||
__writefsdword(const unsigned long Offset, const uint32_t Data)
|
||||
{
|
||||
__asm__ ("movl %[Data], %%fs:%a[Offset]"
|
||||
:
|
||||
: [Offset] "ir" (Offset), [Data] "ir" (Data));
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint8_t
|
||||
__readfsbyte(const unsigned long Offset)
|
||||
{
|
||||
unsigned char value;
|
||||
__asm__ ("movb %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint16_t
|
||||
__readfsword(const unsigned long Offset)
|
||||
{
|
||||
unsigned short value;
|
||||
__asm__ ("movw %%fs:%a[Offset], %[value]"
|
||||
: [value] "=q" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) uint32_t
|
||||
__readfsdword(unsigned long Offset)
|
||||
{
|
||||
unsigned long value;
|
||||
__asm__ ("mov %%fs:%a[Offset], %[value]"
|
||||
: [value] "=r" (value)
|
||||
: [Offset] "ir" (Offset));
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef __SSE3__
|
||||
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
|
||||
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
|
||||
{
|
||||
__m128i data;
|
||||
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
|
||||
_mm_stream_si128_fs2 (__A, data);
|
||||
}
|
||||
|
||||
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
|
||||
{
|
||||
__asm__(".byte 0x64"); // fs prefix
|
||||
__builtin_ia32_clflush (__A);
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
|
||||
{
|
||||
__builtin_ia32_mfence ();
|
||||
}
|
||||
|
||||
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
|
||||
{
|
||||
__builtin_ia32_sfence ();
|
||||
}
|
||||
#endif /* __SSE3__ */
|
||||
|
||||
#endif /* defined (__GNUC__) */
|
||||
@ -33,7 +33,7 @@ ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD
|
||||
|
||||
AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
|
||||
|
||||
AGESA_INC = -I$(obj)
|
||||
AGESA_INC = -I$(obj) -I$(src)/vendorcode/amd/include
|
||||
|
||||
AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR)
|
||||
AGESA_INC += -I$(AGESA_ROOT)/binaryPI
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user