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amdblocks/acpimmio: Unify BIOSRAM usage

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All AMD CPU families supported in coreboot have BIOSRAM space. Looking at
the source code, every family could have the same API to save and restore
cbmem top or UMA base and size.

Unify BIOSRAM layout and add implementation for cbmem top and UMA storing.
Also replace the existing implementation of cbmem top and UMA with the
BIOSRAM access.

TEST=boot PC Engines apu1 and apu2

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
2019-12-01 18:14:39 +01:00
committed by Kyösti Mälkki
parent 73a544d453
commit f65c1e4088
15 changed files with 72 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/southbridge/amd/agesa/hudson/ramtop.c
View File

@@ -16,7 +16,6 @@
#include <stdint.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include "hudson.h"
int acpi_get_sleep_type(void)
@@ -25,27 +24,3 @@ int acpi_get_sleep_type(void)
tmp = ((tmp & (7 << 10)) >> 10);
return (int)tmp;
}
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
uintptr_t restore_top_of_low_cacheable(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return xdata;
}

24
src/southbridge/amd/cimx/sb800/ramtop.c
View File

@@ -25,27 +25,3 @@ int acpi_get_sleep_type(void)
tmp = ((tmp & (7 << 10)) >> 10);
return (int)tmp;
}
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
uintptr_t restore_top_of_low_cacheable(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi * 8);
xnvram_pos++;
}
return xdata;
}