intel: Use CF9 reset (part 2)

Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Kconfig

@@ -104,7 +104,8 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select UDK_2015_BINDING if !SOC_INTEL_GLK
 	select UDK_2017_BINDING if SOC_INTEL_GLK
-	select HAVE_HARD_RESET
+	select SOC_INTEL_COMMON_RESET
+	select HAVE_CF9_RESET_PREPARE
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select HAVE_FSP_GOP
 	select NO_UART_ON_SUPERIO
@@ -130,10 +131,6 @@ config TPM_ON_FAST_SPI
 	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
 	 TPM transactions are decoded and serialized over the SPI interface.
 
-config SOC_INTEL_COMMON_RESET
-	bool
-	default y
-
 config PCR_BASE_ADDRESS
 	hex
 	default 0xd0000000

src/soc/intel/apollolake/reset.c

@@ -13,12 +13,13 @@
  * GNU General Public License for more details.
  */
 
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <delay.h>
 #include <fsp/util.h>
 #include <intelblocks/pmclib.h>
-#include <reset.h>
 #include <soc/heci.h>
+#include <soc/intel/common/reset.h>
 #include <soc/pm.h>
 #include <timer.h>
 
@@ -27,10 +28,10 @@
 void do_global_reset(void)
 {
 	pmc_global_reset_enable(1);
-	hard_reset();
+	do_full_reset();
 }
 
-void soc_reset_prepare(enum reset_type reset_type)
+void cf9_reset_prepare(void)
 {
 	struct stopwatch sw;
 

src/soc/intel/apollolake/romstage.c

@@ -24,6 +24,7 @@
 #include <bootmode.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/pae.h>
@@ -38,7 +39,6 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/pmclib.h>
 #include <mrc_cache.h>
-#include <reset.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/meminit.h>
@@ -285,7 +285,7 @@ static void check_full_retrain(const FSPM_UPD *mupd)
 
 	if (ps->gen_pmcon1 & WARM_RESET_STS) {
 		printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
-		hard_reset();
+		full_reset();
 	}
 }