sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel: Use CF9 reset (part 2)

Browse Source 
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Rudolph
2018-10-01 19:17:11 +02:00
committed by Patrick Georgi
parent 45022ae056
commit f677d17ab3
23 changed files with 67 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/common/Kconfig
View File

@@ -25,6 +25,7 @@ config DISPLAY_SMM_MEMORY_MAP
config SOC_INTEL_COMMON_RESET
bool
default n
select HAVE_CF9_RESET
config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
bool

2
src/soc/intel/common/block/acpi/acpi.c
View File

@@ -18,7 +18,7 @@
#include <arch/smp/mpspec.h>
#include <bootstate.h>
#include <cbmem.h>
#include <cpu/intel/reset.h>
#include <cf9_reset.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>

33
src/soc/intel/common/reset.c
View File

@@ -1,9 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright 2017 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,21 +13,24 @@
* GNU General Public License for more details.
*/
#include <arch/hlt.h>
#include <arch/io.h>
#include <cpu/intel/reset.h>
#include <arch/cache.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <halt.h>
#include <reset.h>
#if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
void do_hard_reset(void)
{
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
}
#endif
#include "reset.h"
void do_soft_reset(void)
void global_reset(void)
{
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
printk(BIOS_INFO, "%s() called!\n", __func__);
cf9_reset_prepare();
dcache_clean_all();
do_global_reset();
halt();
}
void do_board_reset(void)
{
full_reset();
}

28
src/soc/intel/common/reset.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _INTEL_COMMON_RESET_H_
#define _INTEL_COMMON_RESET_H_
/*
* Implement SoC specific global reset (i.e. a reset of both host and
* ME partitions). Usually the ME is asked to perform the reset first.
* If that doesn't work out, fall back to a manual global reset.
*/
void do_global_reset(void);
/* Prepare for reset, run do_global_reset(), halt. */
__noreturn void global_reset(void);
#endif /* _INTEL_COMMON_RESET_H_ */