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intel: Use CF9 reset (part 2)

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Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Rudolph
2018-10-01 19:17:11 +02:00
committed by Patrick Georgi
parent 45022ae056
commit f677d17ab3
23 changed files with 67 additions and 92 deletions
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5
src/soc/intel/skylake/reset.c
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@ -13,10 +13,11 @@
* GNU General Public License for more details.
*/
#include <cf9_reset.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/pmclib.h>
#include <reset.h>
#include <soc/intel/common/reset.h>
#include <soc/me.h>
#include <soc/pm.h>
#include <timer.h>
@ -32,7 +33,7 @@ static void do_force_global_reset(void)
/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
* to global reset platform */
hard_reset();
do_full_reset();
}
void do_global_reset(void)