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Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT

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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i5000

Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf

Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
2017-10-15 14:58:49 -06:00
committed by Martin Roth
parent 779b32beff
commit f6af8943e2
25 changed files with 0 additions and 3469 deletions
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1
src/cpu/intel/Kconfig
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@ -39,7 +39,6 @@ source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA1155/Kconfig
source src/cpu/intel/socket_LGA771/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA988B/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig

1
src/cpu/intel/Makefile.inc
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@ -31,7 +31,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
#socket_mPGA604_533Mhz

18
src/cpu/intel/socket_LGA771/Kconfig
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@ -1,18 +0,0 @@
config CPU_INTEL_SOCKET_LGA771
bool
select CPU_INTEL_MODEL_6FX
select SSE2
select MMX
select AP_IN_SIPI_WAIT
if CPU_INTEL_SOCKET_LGA771
config DCACHE_RAM_BASE
hex
default 0xfefc0000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif

12
src/cpu/intel/socket_LGA771/Makefile.inc
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@ -1,12 +0,0 @@
subdirs-y += ../model_6ex
subdirs-y += ../model_6fx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
romstage-y += ../car/romstage.c