soc/braswell: assign unique DMA request lines to I2C controllers

Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.

Source: Intel Braswell UEFI reference code

Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier
2017-06-02 14:33:22 -05:00
committed by Martin Roth
parent 9095e2f50e
commit f6cfa71217

View File

@ -187,8 +187,8 @@ Device (I2C2)
{
LPSS_I2C2_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x12, 0x2, Width32Bit, )
FixedDMA (0x13, 0x3, Width32Bit, )
})
Method (_CRS)
@ -246,8 +246,8 @@ Device (I2C3)
{
LPSS_I2C3_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x14, 0x4, Width32Bit, )
FixedDMA (0x15, 0x5, Width32Bit, )
})
Method (_CRS)
@ -305,8 +305,8 @@ Device (I2C4)
{
LPSS_I2C4_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x16, 0x6, Width32Bit, )
FixedDMA (0x17, 0x7, Width32Bit, )
})
Method (_CRS)
@ -364,8 +364,8 @@ Device (I2C5)
{
LPSS_I2C5_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x18, 0x0, Width32Bit, )
FixedDMA (0x19, 0x1, Width32Bit, )
})
Method (_CRS)
@ -423,8 +423,8 @@ Device (I2C6)
{
LPSS_I2C6_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x1A, 0x2, Width32Bit, )
FixedDMA (0x1B, 0x3, Width32Bit, )
})
Method (_CRS)
@ -482,8 +482,8 @@ Device (I2C7)
{
LPSS_I2C7_IRQ
}
FixedDMA (0x10, 0x0, Width32Bit, )
FixedDMA (0x11, 0x1, Width32Bit, )
FixedDMA (0x1C, 0x4, Width32Bit, )
FixedDMA (0x1D, 0x5, Width32Bit, )
})
Method (_CRS)