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mb/google/volteer: Deduplicate lockdown config

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The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.

Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.

Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2021-07-11 02:48:06 +02:00
committed by Michael Niewöhner
parent 5f235b0a3f
commit f7100eb1c9
10 changed files with 0 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/volteer/variants/chronicler/overridetree.cb
View File

@@ -15,7 +15,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -28,7 +27,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50),

2
src/mainboard/google/volteer/variants/collis/overridetree.cb
View File

@@ -23,7 +23,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -33,7 +32,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/copano/overridetree.cb
View File

@@ -18,7 +18,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -28,7 +27,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/delbin/overridetree.cb
View File

@@ -7,7 +7,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -19,7 +18,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/drobit/overridetree.cb
View File

@@ -16,7 +16,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -29,7 +28,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/eldrid/overridetree.cb
View File

@@ -20,7 +20,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -33,7 +32,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/elemi/overridetree.cb
View File

@@ -15,7 +15,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -28,7 +27,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/lindar/overridetree.cb
View File

@@ -16,7 +16,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -27,7 +26,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/volteer/overridetree.cb
View File

@@ -3,7 +3,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -16,7 +15,6 @@ chip soc/intel/tigerlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,

2
src/mainboard/google/volteer/variants/volteer2/overridetree.cb
View File

@@ -6,7 +6,6 @@ chip soc/intel/tigerlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -21,7 +20,6 @@ chip soc/intel/tigerlake
# Depending on whether we use I2C bus 1 or SPI bus 0 for TPM
# communication, that one needs early initialization.
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50),