diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index 2c594658df..04b88ff21f 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -156,9 +156,6 @@ chip soc/intel/cannonlake
 	# Address 0x90: Disabled
 	register "gen4_dec" = "0x00000000"
 
-	# 8254
-	register "clock_gate_8254" = "0"
-
 # PMC (soc/intel/cannonlake/pmc.c)
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f6bc9d85ad..63679a686a 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -241,10 +241,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;
 
-	/* Legacy 8254 timer support */
-	params->Enable8254ClockGating = config->clock_gate_8254;
-	params->Enable8254ClockGatingOnS3 = config->clock_gate_8254;
-
 	/* disable Legacy PME */
 	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));