sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix the indent and whitespace to match LinuxBIOS standards

Browse Source 
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jordan Crouse
2007-05-10 18:16:03 +00:00
committed by Stefan Reinauer
parent 89d7cd2c83
commit f8030bd924
8 changed files with 606 additions and 594 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/northbridge/amd/lx/chip.h
View File

@@ -18,8 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
struct northbridge_amd_lx_config
{
struct northbridge_amd_lx_config {
};

6
src/northbridge/amd/lx/grphinit.c
View File

@@ -23,7 +23,6 @@
#include <cpu/amd/vr.h>
#include <console/console.h>
/*
* This function mirrors the Graphics_Init routine in GeodeROM.
*/
@@ -54,11 +53,10 @@ void graphics_init(void)
* so we can add the real value in megabytes
*/
wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
vrWrite(wClassIndex, wData);
res = vrRead(wClassIndex);
printk_debug("VRC_VG value: 0x%04x\n", res);
}

37
src/northbridge/amd/lx/northbridge.c
View File

@@ -35,7 +35,6 @@
#include "chip.h"
#include "northbridge.h"
/* here is programming for the various MSRs.*/
#define IM_QWAIT 0x100000
@@ -88,8 +87,12 @@ struct msr_defaults {
int msr_no;
msr_t msr;
} msr_defaults[] = {
{0x1700, {.hi = 0, .lo = IM_QWAIT}},
{0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
{
0x1700, {
.hi = 0,.lo = IM_QWAIT}}, {
0x1800, {
.hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =
DMCF_SERIAL_LOAD_MISSES}},
/* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
/* for 180a, for now, we assume VSM will configure it */
/* 180b is left at reset value,a0000-bffff is non-cacheable */
@@ -97,7 +100,6 @@ struct msr_defaults {
/* oops, 180c will be set by cpu bug handling in cpubug.c */
//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
/* 180d is left at default, e0000-fffff is non-cached */
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
/* we will not set 0x180f, the DMM,yet */
//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
@@ -112,8 +114,8 @@ struct msr_defaults {
/* GLIU1 */
P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
{0}
P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {
0}
};
/* todo: add a resource record. We don't do this here because this may be called when
@@ -146,8 +148,6 @@ int sizeram(void)
return sizem;
}
static void enable_shadow(device_t dev)
{
}
@@ -167,7 +167,6 @@ static void northbridge_init(device_t dev)
//msr.hi |= 0x3;
//msr.lo |= 0x30000;
//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
}
@@ -180,8 +179,7 @@ void northbridge_set_resources(struct device *dev)
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
for (resource = &dev->resource[0]; resource < last; resource++) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable
//pci_set_resource(dev, resource);
@@ -192,7 +190,9 @@ void northbridge_set_resources(struct device *dev)
struct bus *bus;
bus = &dev->link[link];
if (bus->children) {
printk_debug("my_dev_set_resources: assign_resources %d\n", bus);
printk_debug
("my_dev_set_resources: assign_resources %d\n",
bus);
assign_resources(bus);
}
}
@@ -230,7 +230,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
@@ -239,12 +238,14 @@ static void pci_domain_read_resources(device_t dev)
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
@@ -252,7 +253,8 @@ static void ram_resource(device_t dev, unsigned long index,
{
struct resource *resource;
if (!sizek) return;
if (!sizek)
return;
resource = new_resource(dev, index);
resource->base = ((resource_t) basek) << 10;
@@ -269,8 +271,7 @@ static void pci_domain_set_resources(device_t dev)
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
mc_dev = dev->link[0].children;
if (mc_dev)
{
if (mc_dev) {
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, 640);

119
src/northbridge/amd/lx/northbridgeinit.c
View File

@@ -33,7 +33,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
struct gliutable {
unsigned long desc_name;
unsigned short desc_type;
@@ -46,18 +45,19 @@ struct gliutable gliu0table[] = {
{.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
{.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */
{.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
GL0_CPU},
{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
};
struct gliutable gliu1table[] = {
{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
{.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
{.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */
{.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
{.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
GL1_GLIU0},
{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */
{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
};
@@ -101,8 +101,8 @@ struct msrinit GeodeLinkPriorityTable [] = {
extern int sizeram(void);
static void
writeglmsr(struct gliutable *gl){
static void writeglmsr(struct gliutable *gl)
{
msr_t msr;
msr.lo = gl->lo;
@@ -111,8 +111,7 @@ writeglmsr(struct gliutable *gl){
printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3
}
static void
ShadowInit(struct gliutable *gl)
static void ShadowInit(struct gliutable *gl)
{
msr_t msr;
@@ -154,7 +153,8 @@ static void SysmemInit(struct gliutable *gl)
gl->desc_name, msr.hi, msr.lo);
}
static void SMMGL0Init(struct gliutable *gl) {
static void SMMGL0Init(struct gliutable *gl)
{
msr_t msr;
int sizebytes = sizeram() << 20;
long offset;
@@ -175,10 +175,12 @@ static void SMMGL0Init(struct gliutable *gl) {
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above
printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
gl->desc_name, msr.hi, msr.lo);
}
static void SMMGL1Init(struct gliutable *gl) {
static void SMMGL1Init(struct gliutable *gl)
{
msr_t msr;
printk_debug("%s:\n", __FUNCTION__);
@@ -190,10 +192,12 @@ static void SMMGL1Init(struct gliutable *gl) {
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
wrmsr(gl->desc_name, msr); // MSR - See table above
printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
gl->desc_name, msr.hi, msr.lo);
}
static void GLIUInit(struct gliutable *gl){
static void GLIUInit(struct gliutable *gl)
{
while (gl->desc_type != GL_END) {
switch (gl->desc_type) {
@@ -237,7 +241,8 @@ static void GLIUInit(struct gliutable *gl){
/* * Modified: */
/* * */
/* ************************************************************************** */
static void GLPCIInit(void){
static void GLPCIInit(void)
{
struct gliutable *gl = 0;
int i;
msr_t msr;
@@ -249,7 +254,9 @@ static void GLPCIInit(void){
/* */
msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
msr.lo = 0; /* 0 */
msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
msr.lo |=
GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +
GLPCI_RC_LOWER_WC_SET;
msrnum = GLPCI_RC0;
wrmsr(msrnum, msr);
@@ -282,8 +289,11 @@ static void GLPCIInit(void){
pal = msr.lo << 12;
msr.hi = pah;
msr.lo = pal;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
msr.lo |=
GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
GLPCI_RC_LOWER_WC_SET;
printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
msr.lo, msr.hi);
msrnum = GLPCI_RC1;
wrmsr(msrnum, msr);
}
@@ -291,10 +301,13 @@ static void GLPCIInit(void){
/* */
/* R2 - GLPCI settings for SMM space */
/* */
msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
msr.hi =
((SMM_OFFSET +
(SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
msr.hi);
msrnum = GLPCI_RC2;
wrmsr(msrnum, msr);
@@ -342,10 +355,14 @@ static void GLPCIInit(void){
/* */
/* Arbiter setup */
enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
enable_preempt =
GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET |
GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;
enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;
nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT );
nic_grants_control =
(0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 <<
GLPCI_ARB_UPPER_H2_SHIFT);
msrnum = GLPCI_ARB;
msr = rdmsr(msrnum);
@@ -382,7 +399,6 @@ static void GLPCIInit(void){
msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
wrmsr(msrnum, msr);
/* Set GLPCI Latency Timer */
msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum);
@@ -393,12 +409,13 @@ static void GLPCIInit(void){
msrnum = GLPCI_SPARE;
msr = rdmsr(msrnum);
msr.lo &= ~0x7;
msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
msr.lo |=
GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET |
GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET |
GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
wrmsr(msrnum, msr);
}
/* ************************************************************************** */
/* * */
/* * ClockGatingInit */
@@ -410,7 +427,8 @@ static void GLPCIInit(void){
/* * Modified: */
/* * */
/* ************************************************************************** */
static void ClockGatingInit (void){
static void ClockGatingInit(void)
{
msr_t msr;
struct msrinit *gating = ClockGatingDefault;
int i;
@@ -427,7 +445,8 @@ static void ClockGatingInit (void){
}
static void GeodeLinkPriority(void){
static void GeodeLinkPriority(void)
{
msr_t msr;
struct msrinit *prio = GeodeLinkPriorityTable;
int i;
@@ -444,28 +463,27 @@ static void GeodeLinkPriority(void){
}
}
/*
* Get the GLIU0 shadow register settings
* If the setShadow function is used then all shadow descriptors
* will stay sync'ed.
*/
static uint64_t getShadow(void){
static uint64_t getShadow(void)
{
msr_t msr;
msr = rdmsr(MSR_GLIU0_SHADOW);
return (((uint64_t) msr.hi) << 32) | msr.lo;
}
/*
* Set the cache RConf registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed.
* This is part of the PCI lockup solution
* Entry: EDX:EAX is the shadow settings
*/
static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo){
static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
{
// ok this is whacky bit translation time.
int bit;
@@ -512,7 +530,6 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo){
wrmsr(CPU_RCONF_E0_FF, msr);
}
/*
* Set the GLPCI registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed.
@@ -529,7 +546,6 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(GLPCI_REN, msr);
}
/*
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Keeps all shadow descriptors sync'ed.
@@ -549,20 +565,24 @@ static void setShadow(uint64_t shadowSettings)
setShadowGLPCI(shadowHi, shadowLo);
for (i = 0; gliutables[i]; i++) {
for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
for (pTable = gliutables[i]; pTable->desc_type != GL_END;
pTable++) {
if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name);
msr.lo = (uint32_t) shadowSettings;
msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX
msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
msr.hi |=
((uint32_t) (shadowSettings >> 32)) &
0x0000FFFF;
wrmsr(pTable->desc_name, msr); // MSR - See the table above
}
}
}
}
static void rom_shadow_settings(void){
static void rom_shadow_settings(void)
{
uint64_t shadowSettings = getShadow();
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes
@@ -571,8 +591,6 @@ static void rom_shadow_settings(void){
setShadow(shadowSettings);
}
/***************************************************************************
*
* L1Init
@@ -609,7 +627,6 @@ static void enable_L1_cache(void)
post_code(0xCE); /* POST_RCONFInitError */
while (1) ;
}
// sysdescfound:
msr = rdmsr(gl->desc_name);
@@ -628,27 +645,32 @@ static void enable_L1_cache(void)
msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
// Set the ROMBASE. This is usually FFFC0000h
msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
msr.hi |=
(ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
// Set ROMBASE cache properties.
msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
// now program RCONF_DEFAULT
wrmsr(CPU_RCONF_DEFAULT, msr);
printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n",msr.hi,msr.lo);
printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
msr.lo);
// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
// Set to match system memory cache properties.
msr = rdmsr(CPU_RCONF_DEFAULT);
SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
msr = rdmsr(CPU_RCONF_BYPASS);
msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
msr.lo =
(msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
wrmsr(CPU_RCONF_BYPASS, msr);
printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
msr.lo);
}
static void enable_L2_cache(void) {
static void enable_L2_cache(void)
{
msr_t msr;
/* Instruction Memory Configuration register
@@ -695,7 +717,8 @@ static void setup_lx_cache(void)
wbinvd();
}
uint32_t get_systop(void) {
uint32_t get_systop(void)
{
struct gliutable *gl = 0;
uint32_t systop;
msr_t msr;
@@ -712,7 +735,8 @@ uint32_t get_systop(void) {
systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
systop += 0x1000; /* 4K */
} else {
systop = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
systop =
((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
}
return systop;
}
@@ -749,4 +773,3 @@ void northbridge_init_early(void)
__asm__ __volatile__("FINIT\n");
printk_debug("Exit %s\n", __FUNCTION__);
}

29
src/northbridge/amd/lx/pll_reset.c
View File

@@ -42,14 +42,18 @@ static void pll_reset(char manualconf)
/* Hold Count - how long we will sit in reset */
msrGlcpSysRstpll.lo = PLLMSRlo;
}
else{
} else {
/*automatic configuration (straps) */
POST_CODE(POST_PLL_STRAP);
msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET);
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
msrGlcpSysRstpll.lo &=
~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |=
(0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo &=
~(RSTPPL_LOWER_COREBYPASS_SET |
RSTPPL_LOWER_MBBYPASS_SET);
msrGlcpSysRstpll.lo |=
RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
}
/* Use SWFLAGS to remember: "we've already been here" */
msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
@@ -68,7 +72,8 @@ static void pll_reset(char manualconf)
return;
}
static unsigned int CPUSpeed(void){
static unsigned int CPUSpeed(void)
{
unsigned int speed;
msr_t msr;
@@ -79,7 +84,8 @@ static unsigned int CPUSpeed(void){
}
return (speed);
}
static unsigned int GeodeLinkSpeed(void){
static unsigned int GeodeLinkSpeed(void)
{
unsigned int speed;
msr_t msr;
@@ -90,15 +96,14 @@ static unsigned int GeodeLinkSpeed(void){
}
return (speed);
}
static unsigned int PCISpeed(void){
static unsigned int PCISpeed(void)
{
msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
return (66);
}
else{
} else {
return (33);
}
}

118
src/northbridge/amd/lx/raminit.c
View File

@@ -22,9 +22,13 @@
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536.h"
static const unsigned char NumColAddr[] = {0x00,0x10,0x11,0x00,0x00,0x00,0x00,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F};
static const unsigned char NumColAddr[] = {
0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
};
static void auto_size_dimm(unsigned int dimm){
static void auto_size_dimm(unsigned int dimm)
{
uint32_t dimm_setting;
uint16_t dimm_size;
uint8_t spd_byte;
@@ -47,7 +51,6 @@ static void auto_size_dimm(unsigned int dimm){
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
/* Field: Banks per SDRAM device */
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
@@ -58,7 +61,6 @@ static void auto_size_dimm(unsigned int dimm){
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
/*; Field: DIMM size
*; EEPROM byte usage: (3) Number or Row Addresses
*; (4) Number of Column Addresses
@@ -66,7 +68,8 @@ static void auto_size_dimm(unsigned int dimm){
*; (31) Module Bank Density
*; Size = Module Density * Module Banks
*/
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)){
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
print_debug("Assymetirc DIMM not compatible\r\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
__asm__ __volatile__("hlt\n");
@@ -86,7 +89,6 @@ static void auto_size_dimm(unsigned int dimm){
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
/*; Field: PAGE size
*; EEPROM byte usage: (4) Number of Column Addresses
*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
@@ -133,8 +135,8 @@ static void auto_size_dimm(unsigned int dimm){
wrmsr(MC_CF07_DATA, msr);
}
static void checkDDRMax(void){
static void checkDDRMax(void)
{
uint8_t spd_byte0, spd_byte1;
uint16_t speed;
@@ -155,7 +157,6 @@ static void checkDDRMax(void){
__asm__ __volatile__("hlt\n");
} */
/* Use the slowest DIMM */
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
@@ -172,10 +173,10 @@ static void checkDDRMax(void){
}
}
const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
static void set_refresh_rate(void){
static void set_refresh_rate(void)
{
uint8_t spd_byte0, spd_byte1;
uint16_t rate0, rate1;
msr_t msr;
@@ -200,14 +201,15 @@ static void set_refresh_rate(void){
}
msr = rdmsr(MC_CF07_DATA);
msr.lo|= ((rate0 * (GeodeLinkSpeed()/2))/16) << CF07_LOWER_REF_INT_SHIFT;
msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
<< CF07_LOWER_REF_INT_SHIFT;
wrmsr(MC_CF07_DATA, msr);
}
const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
static void setCAS(void){
static void setCAS(void)
{
/*;*****************************************************************************
;*
;* setCAS
@@ -241,7 +243,8 @@ static void setCAS(void){
spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
(spd_byte & 0x0F)));
if (dimm_speed >= glspeed) {
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
@@ -250,18 +253,19 @@ static void setCAS(void){
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
if (dimm_speed <= glspeed) {
/* set we can use -.5 timing but not -1 */
spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
/* just want bits in the lower byte since we have to cast to a 32 */
casmap0 &= 0xFF << (--spd_byte);
}
} /*MIN_CYCLE_10 !=0 */
}
else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
} else {
/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
/* just want bits in the lower byte since we have to cast to a 32 */
casmap0 &= 0xFF << (spd_byte);
}
} /*MIN_CYCLE_05 !=0 */
}
else{ /* No DIMM */
} else { /* No DIMM */
casmap0 = 0;
}
@@ -281,46 +285,43 @@ static void setCAS(void){
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
if (dimm_speed <= glspeed) {
/* set we can use -.5 timing but not -1 */
spd_byte =31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
/* just want bits in the lower byte since we have to cast to a 32 */
casmap1 &= 0xFF << (--spd_byte);
}
} /*MIN_CYCLE_10 !=0 */
}
else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
spd_byte = 31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
} else {
/* Timing_05 < GLspeed, can't use -.5 or -1 timing */
spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
/* just want bits in the lower byte since we have to cast to a 32 */
casmap1 &= 0xFF << (spd_byte);
}
} /*MIN_CYCLE_05 !=0 */
}
else{ /* No DIMM */
} else { /* No DIMM */
casmap1 = 0;
}
/********************* CAS_LAT MAP COMPARE ***************************/
if (casmap0 == 0) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
}
else if (casmap1 == 0){
} else if (casmap1 == 0) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
}
else if ((casmap0 &= casmap1)){
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
}
else{
} else {
print_debug("DIMM CAS Latencies not compatible\r\n");
POST_CODE(ERROR_DIFF_DIMMS);
__asm__ __volatile__("hlt\n");
}
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
wrmsr(MC_CF8F_DATA, msr);
}
static void set_latencies(void){
static void set_latencies(void)
{
uint32_t memspeed, dimm_setting;
uint8_t spd_byte0, spd_byte1;
msr_t msr;
@@ -349,7 +350,6 @@ static void set_latencies(void){
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
/* tRP */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
if (spd_byte0 == 0xFF) {
@@ -370,7 +370,6 @@ static void set_latencies(void){
}
dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
/* tRCD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
if (spd_byte0 == 0xFF) {
@@ -391,7 +390,6 @@ static void set_latencies(void){
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
/* tRRD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
if (spd_byte0 == 0xFF) {
@@ -412,12 +410,11 @@ static void set_latencies(void){
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
/* tRC = tRP + tRAS */
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) \
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
<< CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF;
msr.lo |= dimm_setting;
@@ -444,8 +441,7 @@ static void set_latencies(void){
if (((spd_byte0 * memspeed) % 1000)) {
++spd_byte1;
}
}
else{ /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
} else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
}
dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
@@ -463,7 +459,8 @@ static void set_latencies(void){
}
}
static void set_extended_mode_registers(void){
static void set_extended_mode_registers(void)
{
uint8_t spd_byte0, spd_byte1;
msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
@@ -486,7 +483,8 @@ static void set_extended_mode_registers(void){
wrmsr(MC_CF07_DATA, msr);
}
static void EnableMTest (void){
static void EnableMTest(void)
{
msr_t msr;
msr = rdmsr(GLCP_DELAY_CONTROLS);
@@ -497,7 +495,9 @@ static void EnableMTest (void){
wrmsr(GLCP_DELAY_CONTROLS, msr);
msr = rdmsr(MC_CFCLK_DBUG);
msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | CFCLK_UPPER_MTST_RBEX_EN_SET;
msr.hi |=
CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
CFCLK_UPPER_MTST_RBEX_EN_SET;
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
@@ -515,8 +515,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
if (GeodeLinkSpeed() < 334) {
msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
}
else{
} else {
msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
}
wrmsr(msrnum, msr);
@@ -535,7 +534,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
wrmsr(msrnum, msr); */
}
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t spd_byte;
@@ -608,8 +606,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* If both Page Size = "Not Installed" we have a problems and should halt. */
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) \
== ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))){
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
print_debug("No memory in the system\r\n");
POST_CODE(ERROR_NO_DIMMS);
__asm__ __volatile__("hlt\n");
@@ -621,14 +619,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
wrmsr(msrnum, msr);
/* Force Precharge All on next command, EMRS */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
@@ -637,14 +633,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
wrmsr(msrnum, msr);
/* Clear Force Precharge All */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
/* MRS Reset DLL - set */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
@@ -653,21 +647,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
wrmsr(msrnum, msr);
/* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
/* Wait 2 PORT61 ticks. between 15us and 30us */
/* This would be endless if the timer is stuck. */
while ((inb(0x61))) ; /* find the first edge */
while (!(~inb(0x61))) ;
/* Force Precharge All on the next command, auto-refresh */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
/* Manually AUTO refresh #1 */
/* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
msrnum = MC_CF07_DATA;
@@ -683,7 +674,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
/* Manually AUTO refresh */
/* The MC should insert the right delay between the refreshes */
msrnum = MC_CF07_DATA;
@@ -693,7 +683,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CF07_LOWER_REF_TEST_SET;
wrmsr(msrnum, msr);
/* MRS Reset DLL - clear */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
@@ -702,17 +691,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
wrmsr(msrnum, msr);
/* Allow MC to tristate during idle cycles with MTEST OFF */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(msrnum, msr);
/* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)){
if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
(7 << CF07_UPPER_D1_PSZ_SHIFT)) {
msrnum = GLCP_DELAY_CONTROLS;
msr = rdmsr(msrnum);
msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
@@ -724,7 +712,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.hi = 0x200; /* pmode 1=200h */
wrmsr(MC_CF_PMCTR, msr);
/* Set PMode1 Up delay enable */
msrnum = MC_CF1017_DATA;
msr = rdmsr(msrnum);
@@ -765,5 +752,4 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
print_debug("RAM DLL lock\r\n");
}