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spd.h: Move enum ddr3_module_type to ddr3.h

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Move specific enum ddr3_module_type to <device/dram/ddr3.h>.

Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas
2022-12-28 12:33:58 +01:00
parent af6cd3f0b4
commit f82e68c900
7 changed files with 22 additions and 60 deletions
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5
src/include/device/dram/ddr3.h
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@@ -32,10 +32,7 @@
#define SPD_DIMM_PART_LEN 18
/** @} */
/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR3. DDR2 SPDs have a different structure.
*/
/* Byte 3 [3:0]: DDR3 Module type information */
enum spd_dimm_type_ddr3 {
SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,

17
src/include/spd.h
View File

@@ -201,23 +201,6 @@ enum spd_memory_type {
#define SPD_ECC_8BIT (1<<3)
#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
/* Byte 3 [3:0]: DDR3 Module type information */
enum ddr3_module_type {
DDR3_SPD_RDIMM = 0x01,
DDR3_SPD_UDIMM = 0x02,
DDR3_SPD_SODIMM = 0x03,
DDR3_SPD_MICRO_DIMM = 0x04,
DDR3_SPD_MINI_RDIMM = 0x05,
DDR3_SPD_MINI_UDIMM = 0x06,
DDR3_SPD_MINI_CDIMM = 0x07,
DDR3_SPD_72B_SO_UDIMM = 0x08,
DDR3_SPD_72B_SO_RDIMM = 0x09,
DDR3_SPD_72B_SO_CDIMM = 0x0a,
DDR3_SPD_LRDIMM = 0x0b,
DDR3_SPD_16B_SO_DIMM = 0x0c,
DDR3_SPD_32B_SO_RDIMM = 0x0d,
};
/* Byte 3 [3:0]: DDR4 Module type information */
enum ddr4_module_type {
DDR4_SPD_RDIMM = 0x01,