From f83b282856ebf83194fd7e2bd7adb5e65a2bd384 Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Thu, 16 Mar 2023 15:11:36 +0800 Subject: [PATCH] soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment Add UPD parameter for eDP power sequence adjust. The pwr_on_vary_bl_to_blon is set one unit per 4ms. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752 Tested-by: build bot (Jenkins) Reviewed-by: Jason Glenesk --- src/soc/amd/mendocino/chip.h | 4 ++++ src/soc/amd/mendocino/fsp_m_params.c | 1 + 2 files changed, 5 insertions(+) diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f16f5fd4be..774ce5ea59 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -177,6 +177,10 @@ struct soc_amd_mendocino_config { /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ union usb3_force_gen1 usb3_port_force_gen1; + /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to + one per 4ms*/ + uint8_t pwr_on_vary_bl_to_blon; + }; #endif /* MENDOCINO_CHIP_H */ diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 37d4048a80..453ce69788 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -170,6 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) } mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; + mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg);