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mb/google/brask/var/bujia: fix type-c USB2 problem

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Enable type-c port 0 USB2 function.

BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: I0d7adc329a8c26941957d7a7472a5166b07bda5b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82903
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shon Wang 2024-06-04 20:19:09 +08:00 committed by Felix Held
parent 6e755cef04
commit f857d30787
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brya/variants/bujia/overridetree.cb
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@ -29,6 +29,7 @@ chip soc/intel/alderlake
}, },
}" }"
register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface