device/pci_device.c: Improve pci_bridge_route() readability
Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -1499,7 +1499,7 @@ static void pci_bridge_route(struct bus *link, scan_state state)
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{
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{
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struct device *dev = link->dev;
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struct device *dev = link->dev;
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struct bus *parent = dev->bus;
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struct bus *parent = dev->bus;
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u32 reg, buses = 0;
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uint8_t primary, secondary, subordinate;
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if (state == PCI_ROUTE_SCAN) {
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if (state == PCI_ROUTE_SCAN) {
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link->secondary = parent->subordinate + 1;
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link->secondary = parent->subordinate + 1;
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@ -1507,15 +1507,17 @@ static void pci_bridge_route(struct bus *link, scan_state state)
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}
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}
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if (state == PCI_ROUTE_CLOSE) {
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if (state == PCI_ROUTE_CLOSE) {
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buses |= 0xfeff << 8;
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primary = 0;
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secondary = 0xff;
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subordinate = 0xfe;
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} else if (state == PCI_ROUTE_SCAN) {
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} else if (state == PCI_ROUTE_SCAN) {
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buses |= parent->secondary & 0xff;
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primary = parent->secondary;
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buses |= ((u32) link->secondary & 0xff) << 8;
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secondary = link->secondary;
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buses |= 0xff << 16; /* MAX PCI_BUS number here */
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subordinate = 0xff; /* MAX PCI_BUS number here */
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} else if (state == PCI_ROUTE_FINAL) {
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} else if (state == PCI_ROUTE_FINAL) {
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buses |= parent->secondary & 0xff;
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primary = parent->secondary;
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buses |= ((u32) link->secondary & 0xff) << 8;
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secondary = link->secondary;
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buses |= ((u32) link->subordinate & 0xff) << 16;
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subordinate = link->subordinate;
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}
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}
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if (state == PCI_ROUTE_SCAN) {
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if (state == PCI_ROUTE_SCAN) {
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@ -1530,11 +1532,9 @@ static void pci_bridge_route(struct bus *link, scan_state state)
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* transactions will not be propagated by the bridge if it is not
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* transactions will not be propagated by the bridge if it is not
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* correctly configured.
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* correctly configured.
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*/
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*/
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pci_write_config8(dev, PCI_PRIMARY_BUS, primary);
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reg = pci_read_config32(dev, PCI_PRIMARY_BUS);
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pci_write_config8(dev, PCI_SECONDARY_BUS, secondary);
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reg &= 0xff000000;
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pci_write_config8(dev, PCI_SUBORDINATE_BUS, subordinate);
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reg |= buses;
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pci_write_config32(dev, PCI_PRIMARY_BUS, reg);
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if (state == PCI_ROUTE_FINAL) {
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if (state == PCI_ROUTE_FINAL) {
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pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd);
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pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd);
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