From f89cb241eecdf70d9e52c852833c6ed1e3b9632d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= <foss@mniewoehner.de>
Date: Wed, 9 Oct 2019 21:02:36 +0200
Subject: [PATCH] mb/google/glados: port to FSP 2.0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT

TODO:
- testing

Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/glados/Kconfig           |   4 ++
 src/mainboard/google/glados/ramstage.c        |   2 +-
 src/mainboard/google/glados/romstage.c        |  20 ++++-----
 src/mainboard/google/glados/spd/spd.c         |   8 ++--
 src/mainboard/google/glados/spd/spd_util.h    |   2 +-
 .../google/glados/variants/asuka/data.vbt     | Bin 4608 -> 0 bytes
 .../glados/variants/asuka/devicetree.cb       |  41 ++++++------------
 .../google/glados/variants/asuka/variant.c    |  25 +++++------
 .../baseboard/include/baseboard/variant.h     |   2 +-
 .../google/glados/variants/caroline/data.vbt  | Bin 4608 -> 0 bytes
 .../glados/variants/caroline/devicetree.cb    |  41 ++++++------------
 .../google/glados/variants/caroline/variant.c |  25 +++++------
 .../google/glados/variants/cave/data.vbt      | Bin 4608 -> 0 bytes
 .../google/glados/variants/cave/devicetree.cb |  41 ++++++------------
 .../google/glados/variants/cave/variant.c     |  24 +++++-----
 .../google/glados/variants/chell/data.vbt     | Bin 4608 -> 0 bytes
 .../glados/variants/chell/devicetree.cb       |  41 ++++++------------
 .../google/glados/variants/chell/variant.c    |  25 +++++------
 .../glados/variants/glados/devicetree.cb      |  41 ++++++------------
 .../google/glados/variants/glados/variant.c   |  24 +++++-----
 .../google/glados/variants/lars/data.vbt      | Bin 4608 -> 0 bytes
 .../google/glados/variants/lars/devicetree.cb |  41 ++++++------------
 .../google/glados/variants/lars/variant.c     |  24 +++++-----
 .../google/glados/variants/sentry/data.vbt    | Bin 4608 -> 0 bytes
 .../glados/variants/sentry/devicetree.cb      |  41 ++++++------------
 .../google/glados/variants/sentry/variant.c   |  24 +++++-----
 26 files changed, 192 insertions(+), 304 deletions(-)
 delete mode 100644 src/mainboard/google/glados/variants/asuka/data.vbt
 delete mode 100644 src/mainboard/google/glados/variants/caroline/data.vbt
 delete mode 100644 src/mainboard/google/glados/variants/cave/data.vbt
 delete mode 100644 src/mainboard/google/glados/variants/chell/data.vbt
 delete mode 100644 src/mainboard/google/glados/variants/lars/data.vbt
 delete mode 100644 src/mainboard/google/glados/variants/sentry/data.vbt

diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 8e48dc710f..292ba93727 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
 	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_USES_FSP2_0
 	select SOC_INTEL_SKYLAKE
 	select SYSTEM_TYPE_LAPTOP
 
@@ -62,6 +63,9 @@ config DEVICETREE
 	string
 	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
+config INTEL_GMA_VBT_FILE
+	default "3rdparty/fsp/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
+
 config MAX_CPUS
 	int
 	default 8
diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c
index 27d674d713..15912cf862 100644
--- a/src/mainboard/google/glados/ramstage.c
+++ b/src/mainboard/google/glados/ramstage.c
@@ -17,7 +17,7 @@
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
 
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index f2daa38d00..113d28bd50 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -25,18 +25,18 @@
 #include "spd/spd_util.h"
 #include "spd/spd.h"
 
-void mainboard_pre_raminit(struct romstage_params *params)
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
 #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
 	/* Turn on keyboard backlight to indicate we are booting */
-	if (params->power_state->prev_sleep_state != ACPI_S3)
+	const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
+	if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME)
 		google_chromeec_kbbacklight(25);
 #endif
-}
 
-void mainboard_memory_init_params(struct romstage_params *params,
-				  MEMORY_INIT_UPD *memory_params)
-{
 	/* Get SPD index */
 	const gpio_t spd_gpios[] = {
 		GPIO_MEM_CONFIG_0,
@@ -46,9 +46,9 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	};
 	const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 
-	memory_params->MemorySpdDataLen = SPD_LEN;
-	memory_params->DqPinsInterleaved = FALSE;
+	mem_cfg->MemorySpdDataLen = SPD_LEN;
+	mem_cfg->DqPinsInterleaved = FALSE;
 
-	spd_memory_init_params(memory_params, spd_idx);
-	variant_memory_init_params(memory_params, spd_idx);
+	spd_memory_init_params(mupd, spd_idx);
+	variant_memory_init_params(mupd, spd_idx);
 }
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index 9503582c9a..324d3be866 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -83,8 +83,10 @@ __weak int is_dual_channel(const int spd_index)
 }
 
 /* Copy SPD data for on-board memory */
-void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index)
+void spd_memory_init_params(FSPM_UPD *mupd, int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
 	uint8_t *spd_file;
 	size_t spd_file_len;
 
@@ -112,9 +114,9 @@ void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index)
 		die("Invalid SPD data.");
 
 	/* Assume same memory in both channels */
-	memory_params->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset;
 	if (is_dual_channel(spd_index))
-		memory_params->MemorySpdPtr10 = memory_params->MemorySpdPtr00;
+		mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
 
 	mainboard_print_spd_info(spd_file + spd_offset);
 }
diff --git a/src/mainboard/google/glados/spd/spd_util.h b/src/mainboard/google/glados/spd/spd_util.h
index 90dbd5ff98..b1e9a7a8a2 100644
--- a/src/mainboard/google/glados/spd/spd_util.h
+++ b/src/mainboard/google/glados/spd/spd_util.h
@@ -16,6 +16,6 @@
 
 #include <fsp/soc_binding.h>
 
-void spd_memory_init_params(MEMORY_INIT_UPD *, int spd_index);
+void spd_memory_init_params(FSPM_UPD *mupd, int spd_index);
 
 #endif /* SPD_UTIL_H */
diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt
deleted file mode 100644
index 8f2a7b0614404d5a1ba4a78e14a66d0f23b09012..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKUu;ul6hF7Of4_TgcXx+U3eF?q=mu=J118KVw`&J0>sY&vIid+2wCG}CV;g4p
zj~ZvP#9;d1A2dXl_+s#7iSfx8c`+_oRAM4N%8Lo2CMIHh0qXhgy{y%RtikvP<+SHJ
z=lkyI@1AqMf2ZpPI|ne`vo8_p=|Y>bpu@cSJ+(`zGv1fpABzk`_ID=wqCL0(cf#xH
zwMzh5L0Bb+bv+zEGMUSV`Wp#0fxV*#M)J9qSZ?Bp$<Z-PM&lSccrcgGjSo-evX~y+
z6+w=vu+C#6`7G`^cKASUyd4QhCu<CEY2LgAG2GHhUp>5)RJ}di*1mPS!eU*~zTRX!
z5gCa0?ZLi&jK$NDbh@jzGqDeo{e9i>&iFuAOks;*L`TPtkB>a|_#}p+jo3=>*kpp5
zE@O0be5@HG`8@V>n+fdCP2|R(%w?Mu#zD@4*C_x9E~trs09RW9yo+BIoCY`%oGKUy
zh6<?ir%nI^00C6)gbI$Wf`i5yyx<P-k?Tb8qNy9)*d}zsml;r1&m}_Q<N<J*iYg#^
zVi6i}o?CgZ*jCnS=^+Z};5OV8k!xh-_i+V)gxgef0j*b4kDMk_$$Q&MGEMlCN~`OG
zf1ea7hAU6e`|Pj<5I6z&1sx9g>S31{f=ST<&xzY$t#cl{K7<WE6&@l^5ihtHd`0{X
z@pr^O6JI6vxEa(EuO_~axP^E-ag?~1_+jE<V)rq)QgRgd6c7~zTh>|<R42UL2!+%3
z_-T9G_Y+Mv5woRaOLMS_rd0BH;9BYP0F+AJ2e}6ZAyC*t%tq?AWx|xAn6&!?Bzdle
z?0%`_%TTwKK7U=y7GQC+l}hv?lWtW_u7lmQfkkh}^cpjey#S@R6%nR@)!KWF#x?o+
zqBM<Gyan!{sez}%l1tlv@=1`N39El_obxa^=eaD*)crd(o;7uukCj<kVD_<K^{qA_
zWGlP3_5X1O)^x*pU!jN>?oz#(wN@hPZ*Ju7M`=wuymT-afTYUM4Iv0X4A#L4$UxGp
zo4jD&yp<`hZU_--mi)951|Sq9@QL4#QSS^9K;tVQKEQC8X%mb+%kUkheZbhq48LXC
zuZ#&2u9vj!5{pVWB56-c>_rLRleCW{_NjzFN?J)`J{enNEh4iX8IQ`^3o<(?<NLDq
ziOjx`@fTV1D6Ce&`xPy&u(X25740R3y{h1ciuRepzE<$6qSg4>DnIV<Ybif_#IH0t
zTm{Dkp-}5L3mxycOlQxKLpJ4QK_%&`Sx>jz(n)DML6<#`Rz`8iu{^?T4MKQm4TcIU
ztQ^(1op4ywA@k#Wd4%jLFe1>P2WHwVgh1N~(W=kLO>lCA4yu`M9EIKlr&6FB`dHnf
z5A;K>%TumkRR~j<3aW-$fglvk>aR+KcUz_|q=F5`(5bQyLeZ@GWWzmIg%9034E?}d
zt6`iiBe<;!NFH=mlgUH(44z3ry}q+(&jrt9(Y!m!m1^?vOmlHI6RbCMwC93m(^)jD
zQ@P-&CW=r;VRmfpUP5Rp&qdL!Q{-9KbQSC2&Bobtsp++P@{N^?2qKuJF=etE1ii_a
z&rE0aK+38Ifua!U=-}(&CfB5ipjZeltRjj_L6}YAN?q2Y<tU1@AIXP;XPdbm_#(gY
zs&=#&0!O!PGKMyl=R$-U%Ln>Lv;4kjG$2!ex{RvUmVKZ@l>3m_ncSZoK9bAt89to*
z4|J>mE87jvgM0Tp)#PXF_M%wUE64wYUit%7zMtzG?|_p#Nye#C-%FQO7B&j6!9}ro
Y4q#@HZV7d>kM0G&pJ>tErkl&aZ;9f<9{>OV

diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb
index cddb10d11a..27bbebaa57 100644
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -60,20 +60,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -100,19 +100,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c
index fdef81c5cd..75e0ea689d 100644
--- a/src/mainboard/google/glados/variants/asuka/variant.c
+++ b/src/mainboard/google/glados/variants/asuka/variant.c
@@ -18,10 +18,13 @@
 #include <string.h>
 #include <baseboard/variant.h>
 #include <fsp/soc_binding.h>
+#include <soc/romstage.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -39,18 +42,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 int is_dual_channel(const int spd_index)
diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
index 72eef684b8..45636acad2 100644
--- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
+++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
@@ -19,6 +19,6 @@
 
 int is_dual_channel(const int spd_index);
 void mainboard_gpio_smi_sleep(void);
-void variant_memory_init_params(MEMORY_INIT_UPD *memory_params, int spd_index);
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index);
 
 #endif /* GLADOS_VARIANT_H */
diff --git a/src/mainboard/google/glados/variants/caroline/data.vbt b/src/mainboard/google/glados/variants/caroline/data.vbt
deleted file mode 100644
index 02e1cd10f68fba12d9de799f7800043f63b4f2b8..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKU2GIp6h5=FzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sU@1Qg<Z6|(9#xD
z{9}zZAu*VJ@COaiCcYSaX<~dbMqZ3fh{}ujC@&^RG%*q53oxELGxUc>y3zQ9>DfK^
zoO|}pH|J;WowMuu+xsxvwJ#Ox>OhC`pu>#%6pf3iJ=v4ppNRFv_P3{c;$3(i?uNJ2
z8&?4Gg0M=C>UuPJWV}#}^wtq<3cH673>6EFiNe^^<HIAEjwdm8@L-`>7#$oh<T2a7
zD~23XVeQ9;ih0~~?C^oYXe$zsPOCAxwPDLv#Ass^ef8)zQuWqobL+P43QKgvd%Dxf
zRID%Avj=;6F_Fy1ve}OA_S8O1_x5xq+mn4A35Csu5g#5oK05Tolj9hP*I^UgW3vTn
zxs37Q(UAs>6^q!**NkCrVXQFvOd;Q(Fb;AK{B8k2@IX}z1i0P=;Gg}f;5NXG;8wvv
zFjPR5|LO)X01!asPN?A8Cb-D9-Vfdox7;Lx7cJf3iycBYT+D&0`mYcYCm(>vQd9xS
z6Y_-^4QJIgXO+vkE&oM8(w$YvHNpx8xH6vvv~Nu|a+*jb?{B+m{?-4CE>fh|o~3(P
zVRIpH0tgB^917IJE-?b*q6=OWTVSnw2K)hpjR6%NA<ht=_b~W|_&eesh<_ozPVDnC
zs3u-b`~Yzy@pj@kaX0a!#Dm1%V{pxMm3Rq=N`fP+Z3(IyUaN!B8OMIcu?K#pViPe(
zN{+OQ6%3~7^T7@Cs}Pu`|6%TdK?oGKkZ_PX9htJED5jlxA4#680cUQSfgDYn==1lD
z>^#hFHq)dVS#+mrat-XJ4J`WGCf8Vj>;*92Q$&~mR_*LHvTO3qhtgWK;$85DEe(8a
zwp={^o4<tlnXvjt*99Mg3%;wu$(sMB#<Qj_@v$>Y514Z-*mHZFpgJwnat3$?)^x(f
zK&gzE?os`@wRTQw|D5IC$LX1L`RQOV07;dh6Cx0T1gwJ<kb|_<H~GPO^UlwHWhO+Z
zT6F1r7=TEaz{eKaXm*wepzd`LA7VJjv@ynBVE8`MK4$DQhTk*oH^u}BH%QuciNz%x
zlC<X}_KJibO4_Fq`$EE>B+ZmqK*mN{i^;4@#-p<Kvdm7&_>ruAF0-#?{8iR`3aeJ|
zK}Aa{EUVygMSE3YZz%YQqJ62bZxy_*XjMVBDu_FRS|-RI3o7+4Psw#jC{+ioM#n!Y
z)7dlNk}Y{vP)T~KHqcvcaZ#F2(951jE2B8zS{h-h3L!eM1|y{vc8+SBPq^%I$R%Hk
zdufFHDllTOUJspYwh=<jCq%nHBR9c9XrrF#kE77*;dBOcLm#P`^?@$rx;)_tSA;Nu
znXqc8^ALox)%{h7@Im9mrA&CeF>rd$2chh>d@#Jz75LD(!_W^*HyOscIRvlW0m=Oy
z5SPy6q5JyJW}sHzS$1l{Gg-FYo#aX-d3e5|Je3RA8ag_)plZ6yR(DF(tR#v^TWM-!
z`hG&FpQ}aL>Qm$?&twHryi+%IAv3vFPrto#7C{8b$z&x6dc84|o6PH>jNK0cMIqAB
zK_v4QW9dvTdL}Id#YXU81qfHdFqOuYx~#|fRbcs0ru|4hRJJc%t)<Y>md(b%=DAvk
zP-P*|pB*oc;`aNZ&VXDAYI3St&9Ab3phJ{MPVG$ZPY)g`6!#1sF8mKBJg9}V@g?x?
zo}r%ntTSE~=k)pZzo479&_WLYHr)lMc9Jnko%&vSS><7q@FrXq8>RtH&e9#BZV7-;
SqW@nl&Yrq8)aCio8TcItGQ%GL

diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index aabf179b93..6314af8661 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -71,20 +71,20 @@ chip soc/intel/skylake
 	register "SlowSlewRateForSa" = "0"	# Fast/2
 	register "FastPkgCRampDisable" = "0"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -111,19 +111,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c
index ab6bd2c1bd..4338d55602 100644
--- a/src/mainboard/google/glados/variants/caroline/variant.c
+++ b/src/mainboard/google/glados/variants/caroline/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,19 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
-	memory_params->DdrFreqLimit = 1600;
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt
deleted file mode 100644
index 02e1cd10f68fba12d9de799f7800043f63b4f2b8..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKU2GIp6h5=FzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sU@1Qg<Z6|(9#xD
z{9}zZAu*VJ@COaiCcYSaX<~dbMqZ3fh{}ujC@&^RG%*q53oxELGxUc>y3zQ9>DfK^
zoO|}pH|J;WowMuu+xsxvwJ#Ox>OhC`pu>#%6pf3iJ=v4ppNRFv_P3{c;$3(i?uNJ2
z8&?4Gg0M=C>UuPJWV}#}^wtq<3cH673>6EFiNe^^<HIAEjwdm8@L-`>7#$oh<T2a7
zD~23XVeQ9;ih0~~?C^oYXe$zsPOCAxwPDLv#Ass^ef8)zQuWqobL+P43QKgvd%Dxf
zRID%Avj=;6F_Fy1ve}OA_S8O1_x5xq+mn4A35Csu5g#5oK05Tolj9hP*I^UgW3vTn
zxs37Q(UAs>6^q!**NkCrVXQFvOd;Q(Fb;AK{B8k2@IX}z1i0P=;Gg}f;5NXG;8wvv
zFjPR5|LO)X01!asPN?A8Cb-D9-Vfdox7;Lx7cJf3iycBYT+D&0`mYcYCm(>vQd9xS
z6Y_-^4QJIgXO+vkE&oM8(w$YvHNpx8xH6vvv~Nu|a+*jb?{B+m{?-4CE>fh|o~3(P
zVRIpH0tgB^917IJE-?b*q6=OWTVSnw2K)hpjR6%NA<ht=_b~W|_&eesh<_ozPVDnC
zs3u-b`~Yzy@pj@kaX0a!#Dm1%V{pxMm3Rq=N`fP+Z3(IyUaN!B8OMIcu?K#pViPe(
zN{+OQ6%3~7^T7@Cs}Pu`|6%TdK?oGKkZ_PX9htJED5jlxA4#680cUQSfgDYn==1lD
z>^#hFHq)dVS#+mrat-XJ4J`WGCf8Vj>;*92Q$&~mR_*LHvTO3qhtgWK;$85DEe(8a
zwp={^o4<tlnXvjt*99Mg3%;wu$(sMB#<Qj_@v$>Y514Z-*mHZFpgJwnat3$?)^x(f
zK&gzE?os`@wRTQw|D5IC$LX1L`RQOV07;dh6Cx0T1gwJ<kb|_<H~GPO^UlwHWhO+Z
zT6F1r7=TEaz{eKaXm*wepzd`LA7VJjv@ynBVE8`MK4$DQhTk*oH^u}BH%QuciNz%x
zlC<X}_KJibO4_Fq`$EE>B+ZmqK*mN{i^;4@#-p<Kvdm7&_>ruAF0-#?{8iR`3aeJ|
zK}Aa{EUVygMSE3YZz%YQqJ62bZxy_*XjMVBDu_FRS|-RI3o7+4Psw#jC{+ioM#n!Y
z)7dlNk}Y{vP)T~KHqcvcaZ#F2(951jE2B8zS{h-h3L!eM1|y{vc8+SBPq^%I$R%Hk
zdufFHDllTOUJspYwh=<jCq%nHBR9c9XrrF#kE77*;dBOcLm#P`^?@$rx;)_tSA;Nu
znXqc8^ALox)%{h7@Im9mrA&CeF>rd$2chh>d@#Jz75LD(!_W^*HyOscIRvlW0m=Oy
z5SPy6q5JyJW}sHzS$1l{Gg-FYo#aX-d3e5|Je3RA8ag_)plZ6yR(DF(tR#v^TWM-!
z`hG&FpQ}aL>Qm$?&twHryi+%IAv3vFPrto#7C{8b$z&x6dc84|o6PH>jNK0cMIqAB
zK_v4QW9dvTdL}Id#YXU81qfHdFqOuYx~#|fRbcs0ru|4hRJJc%t)<Y>md(b%=DAvk
zP-P*|pB*oc;`aNZ&VXDAYI3St&9Ab3phJ{MPVG$ZPY)g`6!#1sF8mKBJg9}V@g?x?
zo}r%ntTSE~=k)pZzo479&_WLYHr)lMc9Jnko%&vSS><7q@FrXq8>RtH&e9#BZV7-;
SqW@nl&Yrq8)aCio8TcItGQ%GL

diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
index 993cab0cee..22ee80f56d 100644
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 4A    | 24A   | 24A         | 24A         | 24A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c
index d63a298df7..d625f1700a 100644
--- a/src/mainboard/google/glados/variants/cave/variant.c
+++ b/src/mainboard/google/glados/variants/cave/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,18 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/chell/data.vbt b/src/mainboard/google/glados/variants/chell/data.vbt
deleted file mode 100644
index a654a5efd5fb57401c093ce712fbf428ce3709ae..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKU2GIp6h1SvzjtP~(<#cbU_Bzjwm>^upq5%?w!4Kc-O}A|sYOlL!Y<ml(9#xD
z{9}zZX<{(@;13$2O?)x<(!}^=jJz0|5S174QC>`tXksG97hpYiX6O%%bffVH!<jwz
zoO|ZZH|Lx?_ujMX`rG?3)3q-d?dm{>a$vx$_87HGsXft?*&mPgMfbNSdtzO94(^7x
zwCk4va)Pi*i5NyCab!GS2=~?zY!bVN4-6IZjq&{0)8oS<n2IGZdhlSrkRKf!&*w1H
zzblFyQ)TVPh6*{{bL{Ye{Aeo@kU^s{vbAB$R>VkS6a9?HHd2k&NOSA9?JA3R#Cp0@
ziDa}d(X$78dNH2JL^GL=?)Kz9O!fA3CfXBy9dVV-g%KMbIX*h{<Wu7qj@4lky<@Wl
zYPpQD;n9%>j1~&m%g2miZ+<L4`b<98pfV0}7JM!NKyX7<6a=`|1mK(dY2Y%!h2YY_
zL@+f#jo)<vm;eZ%aVInow+SNI*89K{<dz#m@RFsQe6U04f(u#DG~Z=H;^YNzTZ$$i
zc|yJrqv?#g>WmVt*YZ08lJ1N`t`Szi&y|HFp#5sHk<&yPd4J1M3!naHbcrIp`YgT6
z3Y!ao6F@*P;E=x-c1d9vmqd6`YJs(`S@8K0Hu^Pqgg8xn&duN(;_rxmApV8;8nM^I
zpqh9!@dLz-#M_Bu#NEV?5)Tr4j=|NkSmaYcR1_RpZA;Kx@LC-dPdoP0j@|z=O*Rp8
zr0ht`SV2=Rd%bYI{8bRjW#7Zx1CtOaY$5I-bviO>Nl8jM{XUXBR|8JJT=r+F+eFvj
z*Rpdkx7f;MdXYu9tESYzZd$;SuWfRT706zI@_VWT6TqsSwMKSbx$#k2gI2r?o{*)1
zx6PJI+kf*;i0=uje-zJq8JzcC5vFSXn;OrWw#;Q`mOe0NTd@0g+B+FooPjl+aKT?J
z;l+D2Uv{m1ulCPb?tOy3Nzq3eg9%8g0-X?sAjDxEtbi<}th&hu*2%lji^@!hP_^XI
zg)ji&5P^>^wo&g45kTGRAU(uzkm+NLy}<B&rhm-XXAHk*`frR0GH#Id?J|qWI3(-O
z$?O#wKa}-PW%h-PKgoJoW_|@56+No3E(MP&`pXJCso+P7{<*@wR`6Fv_o}Q~#RpYA
zp|XsM$5s7RmA#?jC#wFX%Dz?cnyOa?*s1{T2<Yhmdpw}li|(R$Q7BditU|{(s?gpu
zAS#x;B4{MtRU7D(TRJJtC+M)}(JCknh|42PS0O|O)?m1}!p>1`^9j+O4yEXAaV?LK
zTLoqm)*Hd8W*Z^cd_uD8GjbCwgf^;~{x}Mw9!{mfFpZI#IUndjt}7GnP(=t6m=0;C
zwg5pWS=C>K2p=>~Tug`7n**ojeGp0>%LmglQ-KeiJ51xiOp|Gzok#H46_C>J25I?B
z9=fmpOd4v9oh4^3cqU8M*-5Tcl85ITO4Hd;t!bb$7c`r$l2x73Y*rFQxUD!nGIKv6
z)X&dF$*NP7Y4>CWQM^+(eLg+8)=0g*at=WP*~w%j2u8g*o1M%V!L(fu0!1Ow)<LB3
z5@Y#HF8L-c1l2}xV+9D8Lol7fm4;%(_)}o{P@?rnK2)|Y#MWZ)Xv=1EVDtQ3NKj=V
z(4QR-kK)$rqRxbD5o)rUR?VNXeV|R0NJ;KY?N1FJ$rttv9?t&{Iy|VwwDBeI?4G5X
z{EX9HlIHb=_P?N)Z=%H>0BpJoPVOXQf-3dBbXetJlkg^7k{V_Jrsn9jP`CI&DAND0
P7H3V}9O|9^@)`IYcV5CD

diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index a3797571ff..5b82e5aaad 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c
index 3e8503fe9e..892dbeed38 100644
--- a/src/mainboard/google/glados/variants/chell/variant.c
+++ b/src/mainboard/google/glados/variants/chell/variant.c
@@ -21,15 +21,18 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
 		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
 		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
 		{ 0, 3, 1, 2, 4, 5, 6, 7 },
@@ -41,18 +44,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb
index 1d9e6cdf1f..20166253c9 100644
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -70,20 +70,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -110,19 +110,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c
index d63a298df7..d625f1700a 100644
--- a/src/mainboard/google/glados/variants/glados/variant.c
+++ b/src/mainboard/google/glados/variants/glados/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,18 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)
diff --git a/src/mainboard/google/glados/variants/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt
deleted file mode 100644
index 0aac82c3b18d3bb71258b1a04aaadf8dee2152e9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKUu;ul6hF7Of4_TgcXx+U3eF=UbOW~A0Tbqw+qHw0b*x>-9MOahT6D3nu?;i)
zM~yQfF_=F12My6Bz8HL2Vtg`2UW`kK%8U3YFD6JdF%jbna6R9>m$kT%H5mV3IPLk)
z`Of$C_nq_oJzX=@HHg{Xy{TAlH#(FD9p=>yR4%5jWPf&FA~qP?*Olsz_u@IY7v5H{
zUk1nv!U{R6>(S)lsX{R_&_u8)>>JxZS}e3C3X{)Fjg4bEp2XOJ1BGH?Vq~h2$L!F~
z7;;R7bsZfo=5hDYL;DL89Y{br^~UJtmQ9-xqpfZ9)uUTT)jOi?9b2|3EYThB?@K3B
zvB6~jZtNexL^2!8X1n{kQhPBy(BG5nN)C1>6t)mXd~E#K#OPB`Phlk9gl#m&Mhnz(
z8RKIU<1H8~7IA?0nZ$v@WMSgjLcT>|9ONwc-2#B%fw~w7aIFo%zwlMTZGaoWt%8AI
zsDLVObpsdx2%vH&RB&w(Tx4782XBa5ZV<tXmTvIQ4xt+^<Um#ZmkEiJ55Qw7s(|DP
z`9h3_)9b3!%N~}u2<ReV_d=&vFu+X!B)pcQ3uq5bHFBCrCGVYHlGTN`RQI}J{O6=d
zkzRd{#<RlaLf`}t6m&QkXoQ_&1g1n6yd-Xg)$V!l2N2c=RCtUyLwwG|;9KJFiGL*i
zmG~O5&&!~mcqQ>e#I3~Jh~vb4#E%n?5POfpRnt}COF&c-99eHmP~Gr)6O>Ln_S23%
z@Cz+A5p$&ENXuA5VVXW4TsOZCfob|5<sKM>Kw%3B2dT%ADNBlC+Nlqc<a0Ib)J-#x
zqiP#{{=Sl(gN4Ipnlz9_cd8~gz%Dw#qQ7%yl@-Vy0P}rCglS;)&RHY7Cg0eUR;Oj}
zfj4Yv;On&I;_}~Y3G+K)<xj5jJ_hG~SA-J{|4oh0n!3cto>|&p&b46I@0NFG;N}@v
z)dLp-r7~W;Pxa?k+ii`vXSx4L+LJCnT?_^wsWS9H1VWI2HLwhFkhbzBKUgnswHLLS
z5TS0-Ppe@7B4GlbyxB&zGeiJQZ-Dp+!x5%UGWH_F5194|W1lnpfoZ=pCP=tW(zZz~
zF5#%8Juk6WCHzRzK9ks&68<b{ro;j=w#r&eX1y{Vk+oN3c2dTVW$g=@eIw&<vgT7*
zy@C%bT2f(I1&=A(YYKZ)!A}+KD}{Zh;59|73$hhK+#b|2LH0yYX?A%^u8TscK4>L6
z{t21xo?(}4$t!|N(o?sNUb)4K(teyCdmgQf;;?IJgxNZT=<q6xl$P0Z)YyL9WiN-!
zuk)o5@+-iI!CF0ZqTNOawI3Jl{EXZLH%I8Coaxq4=*@5{1G=G)H!S!-KjgYR?FrX}
zFpZh8YN%BRLfOjxYDD<3b^2l^yw(^#Rq;V6TRER>c;{;Hp=Z0H@1JWkjI$L4ublzO
zL!Me@^56qQXEM;J?<hNK!Dq5;y`AJrE%Wd~OL;aIZZvds)`C{kUAD4Qx#X)Qib!W^
zc6{zZLTIk6McK+z<XO*54g2BUrrGnEnbmswo#hJ%B3P+0&15YIdb2T~o5|~;jGYex
zMIqAF!S};$?nw(lu@O92Lll?8Fq_8Zx~#`5QIzRCk`E={R%<`-O@8ZL?dm9nj%?j%
z3~#Kgg$Q-F5A=^_>2uL!K&}K0IaRH%_&}E^_aU_-y)Qj-xKP|Za;We>sMrBkm+M~!
z@2+{u$<H|DC9$Gc+y8=Y{)wu`=lX_w;N%XHNy^ms&|{T{4Z>S+No<(|II%!?gt{p}
P?*czhv}y0s?aja+nFGQf

diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
index b8871d196d..503cf5a58d 100644
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -58,20 +58,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -98,19 +98,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c
index 37860c3738..c24950d814 100644
--- a/src/mainboard/google/glados/variants/lars/variant.c
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -28,9 +28,11 @@
 #define MEM_SINGLE_CHANB	0xb
 #define MEM_SINGLE_CHANC	0xc
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -58,18 +60,12 @@ void variant_memory_init_params(
 	if (spd_index == K4E6E304EB_MEM_ID)
 		targeted_rcomp = StrengthendRcompTarget;
 
-	memcpy(params->DqByteMapCh0, dq_map[0],
-			sizeof(params->DqByteMapCh0));
-	memcpy(params->DqByteMapCh1, dq_map[1],
-			sizeof(params->DqByteMapCh1));
-	memcpy(params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(params->DqsMapCpu2DramCh0));
-	memcpy(params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(params->DqsMapCpu2DramCh1));
-	memcpy(params->RcompResistor, RcompResistor,
-			sizeof(params->RcompResistor));
-	memcpy(params->RcompTarget, targeted_rcomp,
-			sizeof(params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 int is_dual_channel(const int spd_index)
diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt
deleted file mode 100644
index 0aac82c3b18d3bb71258b1a04aaadf8dee2152e9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4608
zcmeHKUu;ul6hF7Of4_TgcXx+U3eF=UbOW~A0Tbqw+qHw0b*x>-9MOahT6D3nu?;i)
zM~yQfF_=F12My6Bz8HL2Vtg`2UW`kK%8U3YFD6JdF%jbna6R9>m$kT%H5mV3IPLk)
z`Of$C_nq_oJzX=@HHg{Xy{TAlH#(FD9p=>yR4%5jWPf&FA~qP?*Olsz_u@IY7v5H{
zUk1nv!U{R6>(S)lsX{R_&_u8)>>JxZS}e3C3X{)Fjg4bEp2XOJ1BGH?Vq~h2$L!F~
z7;;R7bsZfo=5hDYL;DL89Y{br^~UJtmQ9-xqpfZ9)uUTT)jOi?9b2|3EYThB?@K3B
zvB6~jZtNexL^2!8X1n{kQhPBy(BG5nN)C1>6t)mXd~E#K#OPB`Phlk9gl#m&Mhnz(
z8RKIU<1H8~7IA?0nZ$v@WMSgjLcT>|9ONwc-2#B%fw~w7aIFo%zwlMTZGaoWt%8AI
zsDLVObpsdx2%vH&RB&w(Tx4782XBa5ZV<tXmTvIQ4xt+^<Um#ZmkEiJ55Qw7s(|DP
z`9h3_)9b3!%N~}u2<ReV_d=&vFu+X!B)pcQ3uq5bHFBCrCGVYHlGTN`RQI}J{O6=d
zkzRd{#<RlaLf`}t6m&QkXoQ_&1g1n6yd-Xg)$V!l2N2c=RCtUyLwwG|;9KJFiGL*i
zmG~O5&&!~mcqQ>e#I3~Jh~vb4#E%n?5POfpRnt}COF&c-99eHmP~Gr)6O>Ln_S23%
z@Cz+A5p$&ENXuA5VVXW4TsOZCfob|5<sKM>Kw%3B2dT%ADNBlC+Nlqc<a0Ib)J-#x
zqiP#{{=Sl(gN4Ipnlz9_cd8~gz%Dw#qQ7%yl@-Vy0P}rCglS;)&RHY7Cg0eUR;Oj}
zfj4Yv;On&I;_}~Y3G+K)<xj5jJ_hG~SA-J{|4oh0n!3cto>|&p&b46I@0NFG;N}@v
z)dLp-r7~W;Pxa?k+ii`vXSx4L+LJCnT?_^wsWS9H1VWI2HLwhFkhbzBKUgnswHLLS
z5TS0-Ppe@7B4GlbyxB&zGeiJQZ-Dp+!x5%UGWH_F5194|W1lnpfoZ=pCP=tW(zZz~
zF5#%8Juk6WCHzRzK9ks&68<b{ro;j=w#r&eX1y{Vk+oN3c2dTVW$g=@eIw&<vgT7*
zy@C%bT2f(I1&=A(YYKZ)!A}+KD}{Zh;59|73$hhK+#b|2LH0yYX?A%^u8TscK4>L6
z{t21xo?(}4$t!|N(o?sNUb)4K(teyCdmgQf;;?IJgxNZT=<q6xl$P0Z)YyL9WiN-!
zuk)o5@+-iI!CF0ZqTNOawI3Jl{EXZLH%I8Coaxq4=*@5{1G=G)H!S!-KjgYR?FrX}
zFpZh8YN%BRLfOjxYDD<3b^2l^yw(^#Rq;V6TRER>c;{;Hp=Z0H@1JWkjI$L4ublzO
zL!Me@^56qQXEM;J?<hNK!Dq5;y`AJrE%Wd~OL;aIZZvds)`C{kUAD4Qx#X)Qib!W^
zc6{zZLTIk6McK+z<XO*54g2BUrrGnEnbmswo#hJ%B3P+0&15YIdb2T~o5|~;jGYex
zMIqAF!S};$?nw(lu@O92Lll?8Fq_8Zx~#`5QIzRCk`E={R%<`-O@8ZL?dm9nj%?j%
z3~#Kgg$Q-F5A=^_>2uL!K&}K0IaRH%_&}E^_aU_-y)Qj-xKP|Za;We>sMrBkm+M~!
z@2+{u$<H|DC9$Gc+y8=Y{)wu`=lX_w;N%XHNy^ms&|{T{4Z>S+No<(|II%!?gt{p}
P?*czhv}y0s?aja+nFGQf

diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb
index 7f52586e3d..4c6bbf817a 100644
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -60,20 +60,20 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
+	# VR Settings Configuration for 4 Domains
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
+	#+----------------+-----------+-----------+-------------+----------+
+	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
+	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
+	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
+	#| Psi3Enable     | 1         | 1         | 1           | 1        |
+	#| Psi4Enable     | 1         | 1         | 1           | 1        |
+	#| ImonSlope      | 0         | 0         | 0           | 0        |
+	#| ImonOffset     | 0         | 0         | 0           | 0        |
+	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
+	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
+	#+----------------+-----------+-----------+-------------+----------+
 	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
@@ -100,19 +100,6 @@ chip soc/intel/skylake
 		.voltage_limit = 1520,
 	}"
 
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
 	register "domain_vr_config[VR_GT_UNSLICED]" = "{
 		.vr_config_enable = 1,
 		.psi1threshold = VR_CFG_AMP(20),
diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c
index 101be2a0fb..b77e5edc7f 100644
--- a/src/mainboard/google/glados/variants/sentry/variant.c
+++ b/src/mainboard/google/glados/variants/sentry/variant.c
@@ -21,9 +21,11 @@
 
 #define K4E6E304EE_MEM_ID	0x3
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -51,16 +53,10 @@ void variant_memory_init_params(
 	if (spd_index == K4E6E304EE_MEM_ID)
 		targeted_rcomp = StrengthendRcompTarget;
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, targeted_rcomp,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }