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mb/google/brya: Centralize GPIO configuration in trulo baseboard

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This change moves the GPIO configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.

BUG=b:351976770
TEST=Builds successfully for google/orisa.

Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-07-18 15:52:46 +05:30
parent 1cefae23f8
commit f945afc38d
2 changed files with 13 additions and 20 deletions
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17
src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
View File

@@ -6,10 +6,17 @@
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>
/* TODO: Set the correct values */ /* eSPI virtual wire reporting */
#define EC_SCI_GPI 0 #define EC_SCI_GPI GPE0_ESPI
#define GPIO_PCH_WP 0 /* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
#define GPIO_EC_IN_RW 0 #define GPE_EC_WAKE GPE0_DW2_17
#define GPIO_SLP_S0_GATE 0 /* WP signal to PCH */
#define GPIO_PCH_WP GPP_E3
/* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps, MKBP interrupts */
#define EC_SYNC_IRQ GPD2_IRQ
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_H18
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */

16
src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
View File

@@ -3,20 +3,6 @@
#ifndef VARIANT_GPIO_H #ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H #define VARIANT_GPIO_H
#include <soc/gpe.h> #include <baseboard/gpio.h>
#include <soc/gpio.h>
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
#define GPE_EC_WAKE GPE0_DW2_17
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E3
/* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps, MKBP interrupts */
#define EC_SYNC_IRQ GPD2_IRQ
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_H18
#endif #endif