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sb/intel/bd82x6x/pcie: Use defines

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Use defines instead of magic values.

Test: Lenovo X220 still boots and all PCIe devices are
      still working.

Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
2023-10-08 12:24:43 +02:00
committed by Felix Held
parent 359d8a63fc
commit f94a522086
1 changed files with 7 additions and 7 deletions
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14
src/southbridge/intel/bd82x6x/pcie.c
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@@ -126,17 +126,19 @@ static void pch_pcie_pm_early(struct device *dev)
reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
pci_write_config32(dev, 0xd8, reg32);
cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
/* Adjust ASPM L1 exit latency */
reg32 = pci_read_config32(dev, 0x4c);
reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
reg32 = pci_read_config32(dev, cap + PCI_EXP_LNKCAP);
reg32 &= ~PCI_EXP_LNKCAP_L1EL;
if (RCBA32(CIR9) & (1 << 16)) {
/* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
reg32 |= (1 << 17);
reg32 |= (4 << 15);
} else {
/* Else set ASPM L1 to 2-4us */
reg32 |= (1 << 16);
reg32 |= (2 << 15);
}
pci_write_config32(dev, 0x4c, reg32);
pci_write_config32(dev, cap + PCI_EXP_LNKCAP, reg32);
/*
* PCI device enumeration hasn't started yet, thus any downstream device here
@@ -147,8 +149,6 @@ static void pch_pcie_pm_early(struct device *dev)
child = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
/* Set slot power limit as configured above */
cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP);
if (pci_is_hotplugable(dev))
reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC);