Remove MIPS architecture
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Patrick Georgi
parent
63c444a69b
commit
f96d9051c2
@@ -64,7 +64,7 @@ across architectures.
|
||||
### Mentors
|
||||
* Timothy Pearson <tpearson@raptorengineering.com>
|
||||
|
||||
## Support QEMU AArch64 or MIPS
|
||||
## Support QEMU AArch64
|
||||
Having QEMU support for the architectures coreboot can boot helps with
|
||||
some (limited) compatibility testing: While QEMU generally doesn't need
|
||||
much hardware init, any CPU state changes in the boot flow will likely
|
||||
@@ -105,7 +105,7 @@ would help to ensure code quality and make the runtime code more robust.
|
||||
### Mentors
|
||||
* Werner Zeh <werner.zeh@gmx.net>
|
||||
|
||||
## Port payloads to ARM, AArch64, MIPS or RISC-V
|
||||
## Port payloads to ARM, AArch64 or RISC-V
|
||||
While we have a rather big set of payloads for x86 based platforms, all other
|
||||
architectures are rather limited. Improve the situation by porting a payload
|
||||
to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
|
||||
|
Reference in New Issue
Block a user