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mb/google/rex/variants/deku: Add USB configuration

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+-------------+----------------+------------+
| USB 2.0     | Connector Type | OC Mapping |
+-------------+----------------+------------+
|      1      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      2      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      3      |     Type-C     |    OC-0    |
+-------------+----------------+------------+
|      4      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      5      |     Type-C     |    OC_0    |
+-------------+----------------+------------+
|      6      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      7      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      8      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      9      |     Type-A     |    OC_3    |
+-------------+----------------+------------+
|      10     |       BT       |     NA     |
+-------------+----------------+------------+

+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1     | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
|          1          |       Type-A      |    OC_3    |
+---------------------+-------------------+------------+
|          2          |       Type-A      |    OC_3    |
+---------------------+-------------------+------------+

+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
|   1  |   Type C port 0   |    OC_0    |
+------+-------------------+------------+
|   2  |   Type C port 1   |    OC_0    |
+------+-------------------+------------+
|   3  |   Type C port 2   |    OC_0    |
+------+-------------------+------------+
|   4  |   Type C port 3   |    OC_0    |
+------+-------------------+------------+

BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I743fd82f088a57e906b8b9d0fe2e012d9c5f9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78497
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eran Mitrani
2023-10-23 14:18:08 -07:00
committed by Felix Held
parent b09edd37a9
commit f976470746
1 changed files with 19 additions and 0 deletions
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19
src/mainboard/google/rex/variants/deku/overridetree.cb
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@@ -1,5 +1,24 @@
chip soc/intel/meteorlake chip soc/intel/meteorlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A4
register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1
register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
register "serial_io_i2c_mode" = "{ register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled,