amd/db-ft3b-lc: Add board support
Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
This commit is contained in:
Kyösti Mälkki
@@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* 2013 - 2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -16,6 +17,7 @@
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/pi/BiosCallOuts.h>
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#include <device/azalia.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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@@ -33,7 +35,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD, agesa_ReadSpd_from_cbfs },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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@@ -49,26 +51,41 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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* Realtek ALC272 CODEC Verb Table
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*/
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static const CODEC_ENTRY Alc272_VerbTbl[] = {
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{0x11, 0x411111F0}, // - SPDIF_OUT2
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{0x12, 0x411111F0}, // - DMIC_1/2
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{0x13, 0x411111F0}, // - DMIC_3/4
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{0x14, 0x411111F0}, // Port D - LOUT1
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{0x15, 0x411111F0}, // Port A - LOUT2
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{0x16, 0x411111F0}, //
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{0x17, 0x411111F0}, // Port H - MONO
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{0x18, 0x01a19840}, // Port B - MIC1
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{0x19, 0x411111F0}, // Port F - MIC2
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{0x1a, 0x01813030}, // Port C - LINE1
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{0x1b, 0x411111F0}, // Port E - LINE2
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{0x1d, 0x40251E05}, // - PCBEEP
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{0x1e, 0x01441120}, // - SPDIF_OUT1
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{0x21, 0x01214010}, // Port I - HPOUT
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{0xff, 0xffffffff}
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{ 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */
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{ 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */
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{ 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */
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{ 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */
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{ 0x15, 0x411111F0 }, /* Port A - Surround */
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{ 0x17, 0x411111F0 }, /* Port H - Mono */
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{ 0x18, /* Port B - MIC - combo jack */
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(AZALIA_PINCFG_PORT_JACK << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
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| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_BLACK << 12)
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| (4 << 4)
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| (0 << 0)
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},
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{ 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */
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{ 0x1A, 0x411111F0 }, /* Port C - LINE1 */
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{ 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */
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{ 0x1D, 0x40130605 }, /* - PCBEEP */
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{ 0x1E, 0x411111F0 }, /* - SPDIF_OUT1 */
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{ 0x21, /* Port I - HPout - combo jack */
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(AZALIA_PINCFG_PORT_JACK << 30)
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| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
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| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
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| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
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| (AZALIA_PINCFG_COLOR_BLACK << 12)
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| (4 << 4)
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| (0 << 0)
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},
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{ 0xFF, 0xFFFFFFFF },
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};
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static const CODEC_TBL_LIST CodecTableList[] =
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{
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{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
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{0x10ec0272, Alc272_VerbTbl},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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@@ -141,40 +158,40 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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/* Thermal Zone Parameter */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
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@@ -273,7 +290,14 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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FchParams->Azalia.AzaliaPinCfg = TRUE;
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FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
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.AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03,
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.AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03,
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.AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03,
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.AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03
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};
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FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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@@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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select SPD_CACHE
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config MAINBOARD_DIR
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string
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@@ -18,3 +18,23 @@ romstage-y += OemCustomize.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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## DIMM SPD for on-board memory
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SPD_BIN = $(obj)/spd.bin
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# Order of names in SPD_SOURCES is important!
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SPD_SOURCES = Memphis_MEM4G16D3EABG
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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237
src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
Normal file
237
src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
Normal file
@@ -0,0 +1,237 @@
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#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# LOWCOST board has 2GB using 4 Memphis MEM4G16D3EABG chips
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# The datasheet is available at:
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# http://www.memphis.ag/fileadmin/datasheets/MEM4G16D3EABG_10.pdf
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# SPD contents for LC (LowCost) 4GB DDR3 (1600MHz) soldered down
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# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
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# bits[3:0]: 1 = 128 SPD Bytes Used
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# bits[6:4]: 1 = 256 SPD Bytes Total
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# bit7 : 0 = CRC covers bytes 0 ~ 125
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11
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# 1 SPD Revision -
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# 0x10 = Revision 1.0
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10
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# 2 Key Byte / DRAM Device Type
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# bits[7:0]: 0x0b = DDR3 SDRAM
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0B
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# 3 Key Byte / Module Type
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# bits[3:0]: 1 = RDIMM
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# bits[3:0]: 2 = UDIMM
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# bits[3:0]: 3 = SO-DIMM
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# bits[7:4]: reserved
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03
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
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# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bit7 : reserved
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04
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# 5 SDRAM Addressing
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# bits[2:0]: 1 = 10 Column Address Bits
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# bits[5:3]: 2 = 14 Row Address Bits
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# bits[5:3]: 3 = 15 Row Address Bits
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# bits[7:6]: reserved
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19
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# 6 Module Nominal Voltage, VDD
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# bit0 : 0 = 1.5 V operable
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# bit1 : 0 = NOT 1.35 V operable
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# bit2 : 0 = NOT 1.25 V operable
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# bits[7:3]: reserved
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00
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# 7 Module Organization
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# bits[2:0]: 2 = 16 bits
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# bits[5:3]: 0 = 1 Rank
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# bits[7:6]: reserved
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02
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# 8 Module Memory Bus Width
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# bits[2:0]: 3 = Primary bus width is 64 bits
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# bits[4:3]: 0 = 0 bits (no bus width extension)
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# bits[7:5]: reserved
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03
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# 9 Fine Timebase (FTB) Dividend / Divisor
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# bits[3:0]: 0x02 divisor
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# bits[7:4]: 0x05 dividend
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# 5/2 = 2.5ps
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52
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# 10 Medium Timebase (MTB) Dividend
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# 11 Medium Timebase (MTB) Divisor
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# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
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01 08
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# 12 SDRAM Minimum Cycle Time (tCKmin)
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# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
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0A
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# 13 Reserved
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00
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# 14 CAS Latencies Supported, Least Significant Byte
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# 15 CAS Latencies Supported, Most Significant Byte
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# Cas Latencies of 11 - 5 are supported
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FE 00
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# 16 Minimum CAS Latency Time (tAAmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 17 Minimum Write Recovery Time (tWRmin)
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# 0x78 = tWR of 15ns - All DDR3 speed grades
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78
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# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
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# 0x3C = 7.5ns
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3C
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# 20 Minimum Row Precharge Delay Time (tRPmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 21 Upper Nibbles for tRAS and tRC
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# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
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# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
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11
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# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
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# 0x118 = 35ns - DDR3-1600 (see byte 21)
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2C
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# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
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# 0x186 = 48.75ns - DDR3-1600K
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95
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# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
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# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
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# 0x500 = 160ns - for 2 Gigabit chips
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# 0x820 = 260ns - for 4 Gigabit chips
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20 08
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# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
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# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
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3C
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# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
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# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
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3C
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# 28 Upper Nibble for tFAWmin
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# 29 Minimum Four Activate Window Delay Time (tFAWmin)
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# 0x0140 = 40ns - DDR3-1600, 2 KB page size
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# 0x00F0 = 30ns - DDR3-1600, 2 KB page size
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00 F0
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# 30 SDRAM Optional Feature
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||||
# bit0 : 1= RZQ/6 supported
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# bit1 : 1 = RZQ/7 supported
|
||||
# bits[6:2]: reserved
|
||||
# bit7 : 1 = DLL Off mode supported
|
||||
83
|
||||
|
||||
# 31 SDRAM Thermal and Refresh Options
|
||||
# bit0 : 1 = Temp up to 95c supported
|
||||
# bit1 : 0 = 85-95c uses 2x refresh rate
|
||||
# bit2 : 1 = Auto Self Refresh supported
|
||||
# bit3 : 0 = no on die thermal sensor
|
||||
# bits[6:4]: reserved
|
||||
# bit7 : 0 = partial self refresh supported
|
||||
05
|
||||
|
||||
# 32 Module Thermal Sensor
|
||||
# 0 = Thermal sensor not incorporated onto this assembly
|
||||
00
|
||||
|
||||
# 33 SDRAM Device Type
|
||||
# bits[1:0]: 0 = Signal Loading not specified
|
||||
# bits[3:2]: reserved
|
||||
# bits[6:4]: 0 = Die count not specified
|
||||
# bit7 : 0 = Standard Monolithic DRAM Device
|
||||
00
|
||||
|
||||
# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
|
||||
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
|
||||
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
|
||||
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
|
||||
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
|
||||
00 00 00 00 00
|
||||
|
||||
# 39 - 59 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 60 Raw Card Extension, Module Nominal Height
|
||||
# bits[4:0]: 0 = <= 15mm tall
|
||||
# bits[7:5]: 0 = raw card revision 0-3
|
||||
00
|
||||
|
||||
# 61 Module Maximum Thickness
|
||||
# bits[3:0]: 0 = thickness front <= 1mm
|
||||
# bits[7:4]: 0 = thinkness back <= 1mm
|
||||
00
|
||||
|
||||
# 62 Reference Raw Card Used
|
||||
# bits[4:0]: 0 = Reference Raw card A used
|
||||
# bits[6:5]: 0 = revision 0
|
||||
# bit7 : 0 = Reference raw cards A through AL
|
||||
00
|
||||
|
||||
# 63 Address Mapping from Edge Connector to DRAM
|
||||
# bit0 : 0 = standard mapping (not mirrored)
|
||||
# bits[7:1]: reserved
|
||||
00
|
||||
|
||||
# 64 - 116 (reserved)
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
|
||||
# 0x0001 = AMD
|
||||
00 01
|
||||
|
||||
# 119 Module ID: Module Manufacturing Location - oem specified
|
||||
# 120 Module ID: Module Manufacture Year in BCD
|
||||
# 0x14 = 2014
|
||||
00 14
|
||||
|
||||
# 121 Module ID: Module Manufacture week
|
||||
# 0x12 = 12th week
|
||||
12
|
||||
|
||||
# 122 - 125: Module Serial Number
|
||||
00 00 00 00
|
||||
|
||||
# 126 - 127: Cyclical Redundancy Code
|
||||
00 00
|
||||
@@ -13,7 +13,9 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <AGESA.h>
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
#include <PlatformMemoryConfiguration.h>
|
||||
|
||||
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
|
||||
|
||||
@@ -72,22 +74,10 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
|
||||
/* DP0 to HDMI0/DP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
|
||||
},
|
||||
};
|
||||
|
||||
@@ -120,3 +110,101 @@ OemCustomizeInitEarly (
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
|
||||
//
|
||||
// The following macros are supported (use comma to separate macros):
|
||||
//
|
||||
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
|
||||
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
|
||||
// AGESA will base on this value to disable unused MemClk to save power.
|
||||
// Example:
|
||||
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
|
||||
// Bit AM3/S1g3 pin name
|
||||
// 0 M[B,A]_CLK_H/L[0]
|
||||
// 1 M[B,A]_CLK_H/L[1]
|
||||
// 2 M[B,A]_CLK_H/L[2]
|
||||
// 3 M[B,A]_CLK_H/L[3]
|
||||
// 4 M[B,A]_CLK_H/L[4]
|
||||
// 5 M[B,A]_CLK_H/L[5]
|
||||
// 6 M[B,A]_CLK_H/L[6]
|
||||
// 7 M[B,A]_CLK_H/L[7]
|
||||
// And platform has the following routing:
|
||||
// CS0 M[B,A]_CLK_H/L[4]
|
||||
// CS1 M[B,A]_CLK_H/L[2]
|
||||
// CS2 M[B,A]_CLK_H/L[3]
|
||||
// CS3 M[B,A]_CLK_H/L[5]
|
||||
// Then platform can specify the following macro:
|
||||
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
|
||||
//
|
||||
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
|
||||
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
|
||||
// AGESA will base on this value to tristate unused CKE to save power.
|
||||
//
|
||||
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
|
||||
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused ODT pins to save power.
|
||||
//
|
||||
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
|
||||
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused Chip select to save power.
|
||||
//
|
||||
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
|
||||
// Specifies the number of DIMM slots per channel.
|
||||
//
|
||||
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
|
||||
// Specifies the number of Chip selects per channel.
|
||||
//
|
||||
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
|
||||
// Specifies the number of channels per socket.
|
||||
//
|
||||
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
|
||||
// Specifies DDR bus speed of channel ChannelID on socket SocketID.
|
||||
//
|
||||
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
|
||||
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
|
||||
//
|
||||
// WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Specifies the write leveling seed for a channel of a socket.
|
||||
//
|
||||
// HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Speicifes the HW RXEN training seed for a channel of a socket
|
||||
//
|
||||
|
||||
#define SEED_WL 0x0E
|
||||
WRITE_LEVELING_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
|
||||
SEED_WL),
|
||||
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS (LAYERS_6),
|
||||
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
||||
PSO_END
|
||||
};
|
||||
|
||||
void OemPostParams(AMD_POST_PARAMS *PostParams)
|
||||
{
|
||||
/* Add the memory configuration table needed for soldered down memory */
|
||||
PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Board name: DB-FT3b (Olive Hill+)
|
||||
Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm
|
||||
Board name: DB-FT3b-LC
|
||||
Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm
|
||||
Category: eval
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2013 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
@@ -32,9 +33,9 @@ chip northbridge/amd/pi/00730F01/root_complex
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
device pci 8.0 on end # Platform Security Processor
|
||||
device pci 2.4 off end # Edge Connector
|
||||
device pci 2.5 off end # Edge Connector
|
||||
device pci 8.0 off end # Platform Security Processor
|
||||
end #chip northbridge/amd/pi/00730F01
|
||||
|
||||
chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
@@ -42,18 +43,12 @@ chip northbridge/amd/pi/00730F01/root_complex
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # EHCI #0
|
||||
device pci 13.0 on end # EHCI #1
|
||||
device pci 14.0 on # SMBus
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SMbus
|
||||
device pci 14.0 on end # SMBus
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
device pci 16.0 on end # EHCI #2
|
||||
register "sd_mode" = "3"
|
||||
end #chip southbridge/amd/pi/hudson
|
||||
|
||||
device pci 18.0 on end
|
||||
@@ -62,10 +57,6 @@ chip northbridge/amd/pi/00730F01/root_complex
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
|
||||
end #domain
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -13,18 +14,110 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/pi/s3_resume.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <northbridge/amd/pi/BiosCallOuts.h>
|
||||
#include <cpu/amd/pi/s3_resume.h>
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
#include <southbridge/amd/pi/hudson/hudson.h>
|
||||
#include <southbridge/amd/pi/hudson/pci_devs.h>
|
||||
#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
|
||||
#include <northbridge/amd/pi/00730F01/pci_devs.h>
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
|
||||
/***********************************************************
|
||||
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
|
||||
* This table is responsible for physically routing the PIC and
|
||||
* IOAPIC IRQs to the different PCI devices on the system. It
|
||||
* is read and written via registers 0xC00/0xC01 as an
|
||||
* Index/Data pair. These values are chipset and mainboard
|
||||
* dependent and should be updated accordingly.
|
||||
*
|
||||
* These values are used by the PCI configuration space,
|
||||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*/
|
||||
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
|
||||
#if defined(__GNUC__)
|
||||
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
|
||||
#endif
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/22 INTA-C */
|
||||
[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
|
||||
/* SATA */
|
||||
[0x41] = 0x0F,
|
||||
};
|
||||
|
||||
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
|
||||
#if defined(__GNUC__)
|
||||
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
|
||||
#endif
|
||||
/* INTA# - INTH# */
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
|
||||
/* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
|
||||
/* IMC INT0 - 5 */
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
/* USB Devs 18/19/20/22 INTA-C */
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
|
||||
/* SATA */
|
||||
[0x41] = 0x13,
|
||||
};
|
||||
|
||||
/*
|
||||
* This table defines the index into the picr/intr_data
|
||||
* tables for each device. Any enabled device and slot
|
||||
* that uses hardware interrupts should have an entry
|
||||
* in this table to define its index into the FCH
|
||||
* PCI_INTR register 0xC00/0xC01. This index will define
|
||||
* the interrupt that it should use. Putting PIRQ_A into
|
||||
* the PIN A index for a device will tell that device to
|
||||
* use PIC IRQ 10 if it uses PIN A for its hardware INT.
|
||||
*/
|
||||
static const struct pirq_struct mainboard_pirq_data[] = {
|
||||
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
|
||||
{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
|
||||
{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
|
||||
{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
|
||||
{NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
|
||||
{NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
|
||||
{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
|
||||
{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
|
||||
{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
|
||||
{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
|
||||
{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
|
||||
{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
|
||||
{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
|
||||
{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
|
||||
{SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
|
||||
{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
|
||||
{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
static void pirq_setup(void)
|
||||
{
|
||||
pirq_data_ptr = mainboard_pirq_data;
|
||||
pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
|
||||
intr_data_ptr = mainboard_intr_data;
|
||||
picr_data_ptr = mainboard_picr_data;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
@@ -34,6 +127,9 @@ static void mainboard_enable(device_t dev)
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -23,88 +24,51 @@
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/pi/hudson/hudson.h>
|
||||
|
||||
u8 picr_data[0x54] = {
|
||||
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x03,0x04,0x05,0x07
|
||||
};
|
||||
u8 intr_data[0x54] = {
|
||||
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
#include <southbridge/amd/common/amd_pci_util.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u8 byte;
|
||||
|
||||
/* Intialize the MP_Table */
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
* Type 0: Processor Entries:
|
||||
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
|
||||
* CPU Signature (Stepping, Model, Family),
|
||||
* Feature Flags
|
||||
*/
|
||||
smp_write_processors(mc);
|
||||
|
||||
/*
|
||||
* Type 1: Bus Entries:
|
||||
* Bus ID, Bus Type
|
||||
*/
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/*
|
||||
* Type 2: I/O APICs:
|
||||
* APIC ID, Version, APIC Flags:EN, Address
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
outb(picr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* APIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
/*
|
||||
* Type 3: I/O Interrupt Table Entries:
|
||||
* Int Type, Int Polarity, Int Level, Source Bus ID,
|
||||
* Source Bus IRQ, Dest APIC ID, Dest PIN#
|
||||
*/
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
@@ -113,69 +77,47 @@ static void *smp_write_config_table(void *v)
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
|
||||
/* APU Internal Graphic Device */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* SMBUS / ACPI */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
|
||||
/* Southbridge HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
|
||||
/* SATA */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
/* on board NIC & Slot PCIE */
|
||||
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
|
||||
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
|
||||
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
@@ -185,6 +127,6 @@ static void *smp_write_config_table(void *v)
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
||||
@@ -68,16 +68,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
|
||||
|
||||
/*
|
||||
* This refers to LpcClkDrvSth settling time. Without this setting, processor
|
||||
* initialization is slow or incorrect, so this wait has been replicated from
|
||||
* earlier development boards.
|
||||
*/
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 200000; i++) inb(0xCD6);
|
||||
}
|
||||
|
||||
post_code(0x37);
|
||||
AGESAWRAPPER(amdinitreset);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user