armv7: add new dcache and MMU setup functions
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks
committed by
Ronald G. Minnich
Ronald G. Minnich
parent
04d352db41
commit
f9be756b55
@@ -53,12 +53,14 @@ void main(void)
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armv7_invalidate_caches();
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/*
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* Re-enable caches and branch prediction. MMU will be set up later.
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* Re-enable icache and branch prediction. MMU and dcache will be
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* set up later.
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*
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* Note: If booting from USB, we need to disable branch prediction
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* before copying from USB into RAM (FIXME: why?)
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*/
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sctlr = read_sctlr();
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sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I;
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sctlr |= SCTLR_Z | SCTLR_I;
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write_sctlr(sctlr);
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if (boot_cpu()) {
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@@ -108,6 +108,32 @@ static inline void tlbiall(void)
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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}
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/* write data access control register (DACR) */
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static inline void write_dacr(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
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}
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/* write translation table base register 0 (TTBR0) */
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static inline void write_ttbr0(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
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}
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/* read translation table base control register (TTBCR) */
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static inline uint32_t read_ttbcr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
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return val;
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}
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/* write translation table base control register (TTBCR) */
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static inline void write_ttbcr(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
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}
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/*
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* Low-level cache maintenance operations
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*/
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@@ -224,6 +250,12 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
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/* dcache invalidate all (on current level given by CCSELR) */
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void dcache_invalidate_all(void);
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/* dcache and MMU disable */
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void dcache_mmu_disable(void);
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/* dcache and MMU enable */
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void dcache_mmu_enable(void);
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/* icache invalidate all (on current level given by CSSELR) */
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void icache_invalidate_all(void);
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@@ -237,7 +269,17 @@ void tlb_invalidate_all(void);
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/* invalidate all caches on ARMv7 */
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void armv7_invalidate_caches(void);
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/* MMU setup by modified virtual address */
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void mmu_setup_by_mva(unsigned long start, unsigned long size);
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/* mmu initialization (set page table address, set permissions, etc) */
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void mmu_init(void);
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enum dcache_policy {
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DCACHE_OFF,
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DCACHE_WRITEBACK,
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DCACHE_WRITETHROUGH,
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};
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/* mmu range configuration (set dcache policy) */
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void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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enum dcache_policy policy);
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#endif /* ARMV7_CACHE_H */
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@@ -2,37 +2,6 @@
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#ifndef SYSTEM_H_
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#define SYSTEM_H_
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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@@ -48,58 +17,6 @@
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#define arch_align_stack(x) (x)
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#ifndef __ASSEMBLER__
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#include <arch/cache.h> /* for isb() */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF,
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DCACHE_WRITETHROUGH,
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DCACHE_WRITEBACK,
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};
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/* Size of an MMU section */
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enum {
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MMU_SECTION_SHIFT = 20,
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MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
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};
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/**
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* Change the cache settings for a region.
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*
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* \param start start address of memory region to change
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* \param size size of memory region to change
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* \param option dcache option to select
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*/
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void mmu_set_region_dcache(unsigned long start, int size,
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enum dcache_option option);
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/**
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* Register an update to the page tables, and flush the TLB
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*
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* \param start start address of update in page table
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* \param stop stop address of update in page table
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*/
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void mmu_page_table_flush(unsigned long start, unsigned long stop);
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void mmu_setup(unsigned long start, unsigned long size);
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void v7_inval_tlb(void);
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void arm_init_before_mmu(void);
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/*
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* FIXME: sdelay originally came from arch/arm/cpu/armv7/exynos5/setup.h in
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* u-boot but does not seem specific to exynos5...
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@@ -3,12 +3,8 @@
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bootblock-y += syslib.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-y += cache.c
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bootblock-y += cache_v7.c
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bootblock-y += cache-cp15.c
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romstage-y += cache.c
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romstage-y += cache_v7.c
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romstage-y += cache-cp15.c
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romstage-y += div0.c
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romstage-y += syslib.c
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romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
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@@ -19,8 +15,7 @@ ramstage-y += div0.c
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#ramstage-y += memset.S
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ramstage-y += syslib.c
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ramstage-y += cache.c
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ramstage-y += cache_v7.c
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ramstage-y += cache-cp15.c
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ramstage-y += mmu.c
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#FIXME(dhendrix): should this be a config option?
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romstage-y += eabi_compat.c
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@@ -1,221 +0,0 @@
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <stdlib.h>
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#include <system.h>
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static unsigned int tlb_addr;
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static void cp_delay (void)
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{
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volatile int i;
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/* copro seems to need some delay between reading and writing */
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for (i = 0; i < 100; i++)
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nop();
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asm volatile("" : : : "memory");
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}
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static void set_section_dcache(int section, enum dcache_option option)
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{
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u32 value = section << MMU_SECTION_SHIFT | (3 << 10);
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u32 *page_table;
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unsigned int tlb_size = 4096 * 4;
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/*
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* FIXME(dhendrix): This calculation is from arch/arm/lib/board.c
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* in u-boot. We may need to subtract more due to logging.
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* FIXME(rminnich)
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* The cast avoids an incorrect overflow diagnostic.
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* We really need to start adding ULL to constants that are
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* intrinsically unsigned.
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*/
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tlb_addr = ((u32)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20UL));
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tlb_addr -= tlb_size;
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/* round down to next 64KB limit */
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tlb_addr &= ~(0x10000 - 1);
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page_table = (u32 *)tlb_addr;
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switch (option) {
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case DCACHE_WRITETHROUGH:
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value |= 0x1a;
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break;
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case DCACHE_WRITEBACK:
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value |= 0x1e;
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break;
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case DCACHE_OFF:
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value |= 0x12;
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break;
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}
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page_table[section] = value;
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}
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#if 0
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void __mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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debug("%s: Warning: not implemented\n", __func__);
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}
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#endif
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void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option)
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{
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u32 *page_table = &tlb_addr;
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u32 upto, end;
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end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
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start = start >> MMU_SECTION_SHIFT;
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debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n",
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start, size, option);
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for (upto = start; upto < end; upto++)
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set_section_dcache(upto, option);
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mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
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}
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/**
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* dram_bank_mmu_set - set up the data cache policy for a given dram bank
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*
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* @start: virtual address start of bank
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* @size: size of bank (in bytes)
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*/
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static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size)
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{
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int i;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = start >> 20; i < (start + size) >> 20; i++) {
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#if defined(CONFIG_ARM_DCACHE_POLICY_WRITEBACK)
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set_section_dcache(i, DCACHE_WRITEBACK);
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#elif defined(CONFIG_ARM_DCACHE_POLICY_WRITETHROUGH)
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set_section_dcache(i, DCACHE_WRITETHROUGH);
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#else
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#error "Must define dcache policy."
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#endif
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}
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}
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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inline void mmu_setup(unsigned long start, unsigned long size_mb)
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{
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int i;
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u32 reg;
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// arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < 4096; i++)
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set_section_dcache(i, DCACHE_OFF);
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dram_bank_mmu_setup(start, size_mb << 20);
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/* Copy the page table address to cp15 */
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (tlb_addr) : "memory");
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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/* and enable the mmu */
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | CR_M);
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}
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static int mmu_enabled(void)
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{
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return get_cr() & CR_M;
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit)
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{
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uint32_t reg;
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/* The data cache is not active unless the mmu is enabled too */
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if ((cache_bit == CR_C) && !mmu_enabled())
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mmu_setup(start, size);
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | cache_bit);
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}
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/*
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* Big hack warning!
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*
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* Devs like to compile with -O0 to get a nice debugging illusion. But this
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* function does not survive that since -O0 causes the compiler to read the
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* PC back from the stack after the dcache flush. Might it be possible to fix
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* this by flushing the write buffer?
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*/
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static void cache_disable(uint32_t cache_bit) __attribute__ ((optimize(2)));
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/* cache_bit must be either CR_I or CR_C */
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static void cache_disable(uint32_t cache_bit)
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{
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uint32_t reg;
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if (cache_bit == CR_C) {
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/* if cache isn;t enabled no need to disable */
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reg = get_cr();
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if ((reg & CR_C) != CR_C)
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return;
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/* if disabling data cache, disable mmu too */
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cache_bit |= CR_M;
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}
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reg = get_cr();
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cp_delay();
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if (cache_bit == (CR_C | CR_M))
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flush_dcache_all();
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set_cr(reg & ~cache_bit);
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}
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void icache_enable(unsigned long start, unsigned long size)
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{
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cache_enable(start, size, CR_I);
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}
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void icache_disable(void)
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{
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cache_disable(CR_I);
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}
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int icache_status(void)
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{
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return (get_cr() & CR_I) != 0;
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}
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void dcache_enable(unsigned long start, unsigned long size)
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{
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cache_enable(start, size, CR_C);
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}
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void dcache_disable(void)
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{
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cache_disable(CR_C);
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}
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int dcache_status(void)
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{
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return (get_cr() & CR_C) != 0;
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}
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@@ -204,6 +204,28 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
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dcache_op_mva(addr, len, OP_DCCIMVAC);
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}
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void dcache_mmu_disable(void)
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{
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uint32_t sctlr;
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sctlr = read_sctlr();
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dcache_clean_invalidate_all();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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write_sctlr(sctlr);
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}
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void dcache_mmu_enable(void)
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{
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uint32_t sctlr;
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sctlr = read_sctlr();
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dcache_clean_invalidate_all();
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sctlr |= SCTLR_C | SCTLR_M;
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write_sctlr(sctlr);
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}
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void armv7_invalidate_caches(void)
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{
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uint32_t clidr;
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@@ -252,10 +274,3 @@ void armv7_invalidate_caches(void)
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/* Invalidate TLB */
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tlb_invalidate_all();
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}
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|
||||
/* FIXME: wrapper around imported mmu_setup() for now */
|
||||
extern void mmu_setup(unsigned long start, unsigned long size);
|
||||
void mmu_setup_by_mva(unsigned long start, unsigned long size)
|
||||
{
|
||||
mmu_setup(start, size);
|
||||
}
|
||||
|
||||
@@ -1,339 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <armv7.h>
|
||||
#include <common.h>
|
||||
#include <system.h>
|
||||
#include <utils.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#define ARMV7_DCACHE_INVAL_ALL 1
|
||||
#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
|
||||
#define ARMV7_DCACHE_INVAL_RANGE 3
|
||||
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
|
||||
|
||||
/*
|
||||
* Write the level and type you want to Cache Size Selection Register(CSSELR)
|
||||
* to get size details from Current Cache Size ID Register(CCSIDR)
|
||||
*/
|
||||
static void set_csselr(u32 level, u32 type)
|
||||
{ u32 csselr = level << 1 | type;
|
||||
|
||||
/* Write to Cache Size Selection Register(CSSELR) */
|
||||
asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
|
||||
}
|
||||
|
||||
static u32 get_ccsidr(void)
|
||||
{
|
||||
u32 ccsidr;
|
||||
|
||||
/* Read current CP15 Cache Size ID Register */
|
||||
asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
|
||||
return ccsidr;
|
||||
}
|
||||
|
||||
static u32 get_clidr(void)
|
||||
{
|
||||
u32 clidr;
|
||||
|
||||
/* Read current CP15 Cache Level ID Register */
|
||||
asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
|
||||
return clidr;
|
||||
}
|
||||
|
||||
static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
|
||||
u32 num_ways, u32 way_shift,
|
||||
u32 log2_line_len)
|
||||
{
|
||||
int way, set, setway;
|
||||
|
||||
/*
|
||||
* For optimal assembly code:
|
||||
* a. count down
|
||||
* b. have bigger loop inside
|
||||
*/
|
||||
for (way = num_ways - 1; way >= 0 ; way--) {
|
||||
for (set = num_sets - 1; set >= 0; set--) {
|
||||
setway = (level << 1) | (set << log2_line_len) |
|
||||
(way << way_shift);
|
||||
/* Invalidate data/unified cache line by set/way */
|
||||
asm volatile (" mcr p15, 0, %0, c7, c6, 2"
|
||||
: : "r" (setway));
|
||||
}
|
||||
}
|
||||
/* DSB to make sure the operation is complete */
|
||||
CP15DSB;
|
||||
}
|
||||
|
||||
static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
|
||||
u32 num_ways, u32 way_shift,
|
||||
u32 log2_line_len)
|
||||
{
|
||||
int way, set, setway;
|
||||
|
||||
/*
|
||||
* For optimal assembly code:
|
||||
* a. count down
|
||||
* b. have bigger loop inside
|
||||
*/
|
||||
for (way = num_ways - 1; way >= 0 ; way--) {
|
||||
for (set = num_sets - 1; set >= 0; set--) {
|
||||
setway = (level << 1) | (set << log2_line_len) |
|
||||
(way << way_shift);
|
||||
/*
|
||||
* Clean & Invalidate data/unified
|
||||
* cache line by set/way
|
||||
*/
|
||||
asm volatile (" mcr p15, 0, %0, c7, c14, 2"
|
||||
: : "r" (setway));
|
||||
}
|
||||
}
|
||||
/* DSB to make sure the operation is complete */
|
||||
CP15DSB;
|
||||
}
|
||||
|
||||
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
|
||||
{
|
||||
u32 ccsidr;
|
||||
u32 num_sets, num_ways, log2_line_len, log2_num_ways;
|
||||
u32 way_shift;
|
||||
|
||||
set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
|
||||
|
||||
ccsidr = get_ccsidr();
|
||||
|
||||
log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
|
||||
CCSIDR_LINE_SIZE_OFFSET) + 2;
|
||||
/* Converting from words to bytes */
|
||||
log2_line_len += 2;
|
||||
|
||||
num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
|
||||
CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
|
||||
num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
|
||||
CCSIDR_NUM_SETS_OFFSET) + 1;
|
||||
/*
|
||||
* According to ARMv7 ARM number of sets and number of ways need
|
||||
* not be a power of 2
|
||||
*/
|
||||
log2_num_ways = log_2_n_round_up(num_ways);
|
||||
|
||||
way_shift = (32 - log2_num_ways);
|
||||
if (operation == ARMV7_DCACHE_INVAL_ALL) {
|
||||
v7_inval_dcache_level_setway(level, num_sets, num_ways,
|
||||
way_shift, log2_line_len);
|
||||
} else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
|
||||
v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
|
||||
way_shift, log2_line_len);
|
||||
}
|
||||
}
|
||||
|
||||
static void v7_maint_dcache_all(u32 operation)
|
||||
{
|
||||
u32 level, cache_type, level_start_bit = 0;
|
||||
|
||||
u32 clidr = get_clidr();
|
||||
|
||||
for (level = 0; level < 7; level++) {
|
||||
cache_type = (clidr >> level_start_bit) & 0x7;
|
||||
if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
|
||||
(cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
|
||||
(cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
|
||||
v7_maint_dcache_level_setway(level, operation);
|
||||
level_start_bit += 3;
|
||||
}
|
||||
}
|
||||
|
||||
static void v7_dcache_clean_inval_range(u32 start,
|
||||
u32 stop, u32 line_len)
|
||||
{
|
||||
u32 mva;
|
||||
|
||||
/* Align start to cache line boundary */
|
||||
start &= ~(line_len - 1);
|
||||
for (mva = start; mva < stop; mva = mva + line_len) {
|
||||
/* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
|
||||
asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
|
||||
}
|
||||
}
|
||||
|
||||
static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
|
||||
{
|
||||
u32 mva;
|
||||
|
||||
/*
|
||||
* If start address is not aligned to cache-line do not
|
||||
* invalidate the first cache-line
|
||||
*/
|
||||
if (start & (line_len - 1)) {
|
||||
printk(BIOS_ERR, "%s - start address is not aligned - 0x%08x\n",
|
||||
__func__, start);
|
||||
/* move to next cache line */
|
||||
start = (start + line_len - 1) & ~(line_len - 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* If stop address is not aligned to cache-line do not
|
||||
* invalidate the last cache-line
|
||||
*/
|
||||
if (stop & (line_len - 1)) {
|
||||
printk(BIOS_ERR, "%s - stop address is not aligned - 0x%08x\n",
|
||||
__func__, stop);
|
||||
/* align to the beginning of this cache line */
|
||||
stop &= ~(line_len - 1);
|
||||
}
|
||||
|
||||
for (mva = start; mva < stop; mva = mva + line_len) {
|
||||
/* DCIMVAC - Invalidate data cache by MVA to PoC */
|
||||
asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
|
||||
}
|
||||
}
|
||||
|
||||
static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
|
||||
{
|
||||
u32 line_len = dcache_get_line_size();
|
||||
|
||||
switch (range_op) {
|
||||
case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
|
||||
v7_dcache_clean_inval_range(start, stop, line_len);
|
||||
break;
|
||||
case ARMV7_DCACHE_INVAL_RANGE:
|
||||
v7_dcache_inval_range(start, stop, line_len);
|
||||
break;
|
||||
}
|
||||
|
||||
/* DSB to make sure the operation is complete */
|
||||
CP15DSB;
|
||||
}
|
||||
|
||||
/* Invalidate TLB */
|
||||
void v7_inval_tlb(void)
|
||||
{
|
||||
/* Invalidate entire unified TLB */
|
||||
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
|
||||
/* Invalidate entire data TLB */
|
||||
asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
|
||||
/* Invalidate entire instruction TLB */
|
||||
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
|
||||
/* Full system DSB - make sure that the invalidation is complete */
|
||||
CP15DSB;
|
||||
/* Full system ISB - make sure the instruction stream sees it */
|
||||
CP15ISB;
|
||||
}
|
||||
|
||||
unsigned long dcache_get_line_size(void)
|
||||
{
|
||||
u32 line_len, ccsidr;
|
||||
|
||||
ccsidr = get_ccsidr();
|
||||
line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
|
||||
CCSIDR_LINE_SIZE_OFFSET) + 2;
|
||||
/* Converting from words to bytes */
|
||||
line_len += 2;
|
||||
/* converting from log2(linelen) to linelen */
|
||||
line_len = 1 << line_len;
|
||||
|
||||
return line_len;
|
||||
}
|
||||
|
||||
void invalidate_dcache_all(void)
|
||||
{
|
||||
v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
|
||||
|
||||
v7_outer_cache_inval_all();
|
||||
}
|
||||
|
||||
/*
|
||||
* Performs a clean & invalidation of the entire data cache
|
||||
* at all levels
|
||||
*/
|
||||
void flush_dcache_all(void)
|
||||
{
|
||||
v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
|
||||
|
||||
v7_outer_cache_flush_all();
|
||||
}
|
||||
|
||||
/*
|
||||
* Invalidates range in all levels of D-cache/unified cache used:
|
||||
* Affects the range [start, stop - 1]
|
||||
*/
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
|
||||
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
|
||||
|
||||
v7_outer_cache_inval_range(start, stop);
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush range(clean & invalidate) from all levels of D-cache/unified
|
||||
* cache used:
|
||||
* Affects the range [start, stop - 1]
|
||||
*/
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
|
||||
|
||||
v7_outer_cache_flush_range(start, stop);
|
||||
}
|
||||
|
||||
void arm_init_before_mmu(void)
|
||||
{
|
||||
v7_outer_cache_enable();
|
||||
invalidate_dcache_all();
|
||||
v7_inval_tlb();
|
||||
}
|
||||
|
||||
void mmu_page_table_flush(unsigned long start, unsigned long stop)
|
||||
{
|
||||
flush_dcache_range(start, stop);
|
||||
v7_inval_tlb();
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush range from all levels of d-cache/unified-cache used:
|
||||
* Affects the range [start, start + size - 1]
|
||||
*/
|
||||
void flush_cache(unsigned long start, unsigned long size)
|
||||
{
|
||||
flush_dcache_range(start, start + size);
|
||||
}
|
||||
|
||||
/* Invalidate entire I-cache and branch predictor array */
|
||||
void invalidate_icache_all(void)
|
||||
{
|
||||
/*
|
||||
* Invalidate all instruction caches to PoU.
|
||||
* Also flushes branch target cache.
|
||||
*/
|
||||
asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
|
||||
|
||||
/* Invalidate entire branch predictor array */
|
||||
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
|
||||
|
||||
/* Full system DSB - make sure that the invalidation is complete */
|
||||
CP15DSB;
|
||||
|
||||
/* ISB - make sure the instruction stream sees it */
|
||||
CP15ISB;
|
||||
}
|
||||
132
src/arch/armv7/lib/mmu.c
Normal file
132
src/arch/armv7/lib/mmu.c
Normal file
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2013 Google Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <types.h>
|
||||
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#include <arch/cache.h>
|
||||
|
||||
#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */
|
||||
|
||||
static uintptr_t ttb_addr;
|
||||
|
||||
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
|
||||
enum dcache_policy policy)
|
||||
{
|
||||
unsigned int i;
|
||||
uint32_t attr;
|
||||
uint32_t *ttb_entry = (uint32_t *)ttb_addr;
|
||||
const char *str = NULL;
|
||||
|
||||
/*
|
||||
* Section entry bits:
|
||||
* 31:20 - section base address
|
||||
* 18 - 0 to indicate normal section (versus supersection)
|
||||
* 17 - nG, 0 to indicate page is global
|
||||
* 16 - S, 0 for non-shareable (?)
|
||||
* 15 - APX, 0 for full access
|
||||
* 14:12 - TEX, 0b000 for outer and inner write-back
|
||||
* 11:10 - AP, 0b11 for full access
|
||||
* 9 - P, ? (FIXME: not described or possibly obsolete?)
|
||||
* 8: 5 - Domain
|
||||
* 4 - XN, 1 to set execute-never (and also avoid prefetches)
|
||||
* 3 - C, 1 for cacheable
|
||||
* 2 - B, 1 for bufferable
|
||||
* 1: 0 - 0b10 to indicate section entry
|
||||
*/
|
||||
|
||||
switch(policy) {
|
||||
case DCACHE_OFF:
|
||||
/* XN set to avoid prefetches to uncached/unbuffered regions */
|
||||
attr = (0x3 << 10) | (1 << 4) | 0x2;
|
||||
str = "off";
|
||||
break;
|
||||
case DCACHE_WRITEBACK:
|
||||
attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2;
|
||||
str = "writeback";
|
||||
break;
|
||||
case DCACHE_WRITETHROUGH:
|
||||
attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2;
|
||||
str = "writethrough";
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "unknown dcache policy: %02x\n", policy);
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n",
|
||||
start_mb << 20, ((start_mb + size_mb) << 20) - 1, str);
|
||||
|
||||
for (i = start_mb; i < start_mb + size_mb; i++)
|
||||
ttb_entry[i] = (i << 20) | attr;
|
||||
}
|
||||
|
||||
void mmu_init(void)
|
||||
{
|
||||
unsigned int ttb_size;
|
||||
uint32_t ttbcr;
|
||||
|
||||
/*
|
||||
* For coreboot's purposes, we will create a simple L1 page table
|
||||
* in RAM with 1MB section translation entries over the 4GB address
|
||||
* space.
|
||||
* (ref: section 10.2 and example 15-4 in Cortex-A series
|
||||
* programmer's guide)
|
||||
*
|
||||
* FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to
|
||||
* 512 bytes. So add double the space in cbmem and fix-up the pointer.
|
||||
*/
|
||||
ttb_size = L1_TLB_ENTRIES * sizeof(unsigned long);
|
||||
ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2);
|
||||
ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size);
|
||||
printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr);
|
||||
|
||||
/*
|
||||
* Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0
|
||||
* table size is 16KB and has indices VA[31:20].
|
||||
*
|
||||
* ref: Arch Ref. Manual for ARMv7-A, B3.5.4,
|
||||
*/
|
||||
ttbcr = read_ttbcr();
|
||||
ttbcr &= ~(0x3);
|
||||
write_ttbcr(ttbcr);
|
||||
|
||||
/*
|
||||
* Translation table base 0 address is in bits 31:14-N, where N is given
|
||||
* by bits 2:0 in TTBCR (which we set to 0). All lower bits in this
|
||||
* register should be zero for coreboot.
|
||||
*/
|
||||
write_ttbr0(ttb_addr);
|
||||
|
||||
/* disable domain-level checking of permissions */
|
||||
write_dacr(~0);
|
||||
}
|
||||
Reference in New Issue
Block a user