mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC

1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
   PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.

Tested on OCP Tioga Pass.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/ocp/tiogapass/Kconfig

@@ -6,8 +6,10 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_TABLES
-	select MAINBOARD_USES_FSP2_0
 	select IPMI_KCS
+	select MAINBOARD_USES_FSP2_0
+	select OCP_DMI
+	select PARALLEL_MP_AP_WORK
 	select SOC_INTEL_SKYLAKE_SP
 	select SUPERIO_ASPEED_AST2400
 

src/mainboard/ocp/tiogapass/Makefile.inc

@@ -1,7 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
 bootblock-y += bootblock.c
-ramstage-y += ramstage.c
+ramstage-y += ramstage.c ipmi.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)

src/mainboard/ocp/tiogapass/ipmi.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_kcs.h>
+
+#include "ipmi.h"
+
+void ipmi_set_ppin(struct ppin_req *req)
+{
+	int ret;
+	struct ipmi_rsp rsp;
+
+	ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN,
+			(const unsigned char *) req, sizeof(*req),
+			(unsigned char *) &rsp, sizeof(rsp));
+
+	if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) {
+		printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
+			__func__, ret, rsp.completion_code);
+		return;
+	}
+	printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n");
+}

src/mainboard/ocp/tiogapass/ipmi.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef TIOGAPASS_IPMI_H
+#define TIOGAPASS_IPMI_H
+#include <types.h>
+
+#define IPMI_NETFN_OEM 0x30
+#define IPMI_OEM_SET_PPIN 0x77
+
+/* PPIN for 2 CPU IPMI request */
+struct ppin_req {
+	uint32_t cpu0_lo;
+	uint32_t cpu0_hi;
+	uint32_t cpu1_lo;
+	uint32_t cpu1_hi;
+} __packed;
+/* Send CPU0 and CPU1 PPIN to BMC */
+void ipmi_set_ppin(struct ppin_req *req);
+#endif

src/mainboard/ocp/tiogapass/ramstage.c

@@ -1,9 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #include <soc/ramstage.h>
 #include <bootstate.h>
+#include <drivers/ipmi/ipmi_ops.h>
+#include <drivers/ocp/dmi/ocp_dmi.h>
 #include <gpio.h>
+#include <soc/ramstage.h>
 #include <soc/lewisburg_pch_gpio_defs.h>
 
+#include "ipmi.h"
+
+extern struct fru_info_str fru_strings;
+
 void mainboard_silicon_init_params(FSPS_UPD *params)
 {
 }
@@ -14,4 +22,42 @@ static void pull_post_complete_pin(void *unused)
 	gpio_output(GPP_B20, 0);
 }
 
+
+static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t)
+{
+	/* OEM string 1 to 6 */
+	ocp_oem_smbios_strings(dev, t);
+
+	/* OEM string 7 */
+	if (fru_strings.board_info.custom_count > 1 &&
+			*(fru_strings.board_info.board_custom + 1) != NULL)
+		t->count = smbios_add_oem_string(t->eos,
+			*(fru_strings.board_info.board_custom + 1));
+	else
+		t->count = smbios_add_oem_string(t->eos, TBF);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->get_smbios_strings = tp_oem_smbios_strings,
+	read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings);
+}
+
+static void mainboard_final(void *chip_info)
+{
+	struct ppin_req req;
+
+	req.cpu0_lo = xeon_sp_ppin[0].lo;
+	req.cpu0_hi = xeon_sp_ppin[0].hi;
+	req.cpu1_lo = xeon_sp_ppin[1].lo;
+	req.cpu1_hi = xeon_sp_ppin[1].hi;
+	/* Set PPIN to BMC */
+	ipmi_set_ppin(&req);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+	.final = mainboard_final,
+};
+
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);