soc/intel/cannonlake: add GMA backlight control

src/soc/intel/cannonlake/chip.h

@@ -18,6 +18,7 @@
 #ifndef _SOC_CHIP_H_
 #define _SOC_CHIP_H_
 
+#include <drivers/intel/gma/gma.h>
 #include <intelblocks/cfg.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/gpio.h>
@@ -457,6 +458,9 @@ struct soc_intel_cannonlake_config {
 	 * Only override CPU flex ratio if don't want to boot with non-turbo max.
 	 */
 	uint8_t cpu_ratio_override;
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/graphics.c

@@ -16,7 +16,9 @@
 
 #include <arch/acpi.h>
 #include <bootmode.h>
+#include <cbmem.h>
 #include <console/console.h>
+#include <drivers/intel/gma/gma.h>
 #include <fsp/util.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -26,6 +28,14 @@
 #include <drivers/intel/gma/opregion.h>
 #include <intelblocks/graphics.h>
 #include <types.h>
+#include <soc/nvs.h>
+#include "chip.h"
+
+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t *gnvs_ptr = gnvs;
+	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
+}
 
 uintptr_t fsp_soc_get_igd_bar(void)
 {
@@ -73,12 +83,14 @@ void graphics_soc_init(struct device *dev)
 		/* Initialize PCI device, load/execute BIOS Option ROM */
 		pci_dev_init(dev);
 	}
+	intel_gma_restore_opregion();
 }
 
 uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
 		uintptr_t current, struct acpi_rsdp *rsdp)
 {
 	igd_opregion_t *opregion;
+	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
 	opregion = (igd_opregion_t *)current;
@@ -86,7 +98,17 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
 	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
 		return current;
 
+	if (gnvs)
+		gnvs->aslb = (u32)(uintptr_t)opregion;
+
 	current += sizeof(igd_opregion_t);
 
 	return acpi_align_current(current);
 }
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(struct device *device)
+{
+	struct soc_intel_apollolake_config *chip = device->chip_info;
+	return &chip->gfx;
+}

src/soc/intel/common/block/acpi/acpi/globalnvs.asl

@@ -50,6 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	E4GM,	8,	// 0x30 - Enable above 4GB MMIO Resource
 	A4GB,	64,	// 0x31 - 0x38 Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x39 - 0x40 Length of above 4GB MMIO Resource
+	ASLB,	32,	// 0x41 - 0x44 IGD OpRegion Base Address
 
 	/* ChromeOS specific */
 	Offset (0x100),

src/soc/intel/common/block/include/intelblocks/nvs.h

@@ -41,7 +41,8 @@ typedef struct global_nvs_t {
 	u8	e4gm; /* 0x30 - Enable above 4GB MMIO Resource */
 	u64	a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */
 	u64	a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */
-	u8	unused[191];
+	u32 aslb; /* 0x41 - 0x44 IGD OpRegion Base Address */
+	u8	unused[187];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t	chromeos;