From fa66d33336fcf4358c1bacd84ae9427f8dfb59ba Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 29 Jul 2024 13:37:36 -0600 Subject: [PATCH] soc/intel/adl: Update DCACHE_BSP_STACK_SIZE During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 470dbf4d8e..632798e6a1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -191,12 +191,12 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x80400 + default 0x88000 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement - (~1KiB). + (~32KiB). config FSP_TEMP_RAM_SIZE hex