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Alot of it is trivial clean ups and 830 is now able to initialize one row/side of memory at a time.

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Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
2010-02-01 22:51:18 +00:00
committed by Joseph Smith
parent 14be4d0d52
commit fa742da56b
4 changed files with 206 additions and 154 deletions
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11
src/northbridge/intel/i82830/raminit.h
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@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
* Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,12 +21,13 @@
#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H
/* 82830 Northbridge PCI device */
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
struct mem_controller {
device_t d0;
uint16_t channel0[DIMM_SOCKETS];
};
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */