soc/intel: Rename some SMM support functions

Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.

Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/cpu.c

@@ -17,7 +17,9 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
@@ -25,7 +27,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <reg_script.h>
 
 #include <soc/iosf.h>
@@ -198,10 +199,10 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
 
 void baytrail_init_cpus(struct device *dev)

src/soc/intel/baytrail/gpio.c

@@ -190,7 +190,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 			route_reg |= ROUTE_SCI << (2 * (i + 8));
 		}
 	}
-	southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
+	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
 static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],

src/soc/intel/baytrail/include/soc/smm.h

@@ -16,6 +16,8 @@
 #ifndef _BAYTRAIL_SMM_H_
 #define _BAYTRAIL_SMM_H_
 
+#include <types.h>
+
 /* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
  * is included after chipset code. This causes the chipset's Kconfig to be
  * clobbered by the arch/x86/Kconfig if they have the same name. */
@@ -29,17 +31,12 @@ static inline int smm_region_size(void)
 
 uintptr_t smm_region_start(void);
 
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
-
 enum {
 	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
 	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
 	SMM_SAVE_PARAM_COUNT
 };
 
+void smm_southcluster_save_param(int param, uint32_t data);
+
 #endif /* _BAYTRAIL_SMM_H_ */

src/soc/intel/baytrail/pcie.c

@@ -215,7 +215,7 @@ static void byt_pcie_enable(struct device *dev)
 		strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
 
 		if (config->pcie_wake_enable)
-			southcluster_smm_save_param(
+			smm_southcluster_save_param(
 				SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
 	}
 

src/soc/intel/baytrail/smm.c

@@ -20,6 +20,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
 #include <soc/smm.h>
@@ -27,12 +28,12 @@
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
 
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
 	smm_save_params[param] = data;
 }
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -57,7 +58,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
 	u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
 
 	/* Enable SMI generation:
 	 *  - on APMC writes (io 0xb2)