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soc/intel: Rename some SMM support functions

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Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.

Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-14 05:41:41 +03:00
parent f091f4daf7
commit faf20d30a6
49 changed files with 100 additions and 211 deletions
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15
src/soc/intel/fsp_baytrail/smm.c
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@@ -20,21 +20,22 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/smm_reloc.h>
#include <bootstate.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/pmc.h>
#include <soc/smm.h>
/* Save the gpio route register. The settings are committed from
* southcluster_smm_enable_smi(). */
* smm_southbridge_enable_smi(). */
static uint32_t gpio_route;
void southcluster_smm_save_gpio_route(uint32_t route)
void smm_southcluster_save_gpio_route(uint32_t route)
{
gpio_route = route;
}
void southcluster_smm_clear_state(void)
void smm_southbridge_clear_state(void)
{
uint32_t smi_en;
@@ -59,7 +60,7 @@ void southcluster_smm_clear_state(void)
clear_pmc_status();
}
static void southcluster_smm_route_gpios(void)
static void smm_southcluster_route_gpios(void)
{
u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -84,7 +85,7 @@ static void southcluster_smm_route_gpios(void)
outl(alt_gpio_reg, alt_gpio_smi);
}
void southcluster_smm_enable_smi(void)
void smm_southbridge_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
southcluster_smm_route_gpios();
smm_southcluster_route_gpios();
/* Enable SMI generation:
* - on APMC writes (io 0xb2)