soc/intel: Rename some SMM support functions

Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.

Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/haswell.h

@@ -154,13 +154,6 @@ void intel_cpu_haswell_finalize_smm(void);
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
 /* Determine if HyperThreading is disabled. The variable is not valid until
  * setup_ap_init() has been called. */
 #endif

src/cpu/intel/haswell/haswell_init.c

@@ -24,6 +24,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
@@ -761,7 +762,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();

src/cpu/intel/haswell/smmrelocate.c

@@ -25,6 +25,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <southbridge/intel/lynxpoint/pch.h>
@@ -325,7 +326,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 void smm_initialize(void)
 {
 	/* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
 
 	/*
 	 * Run the relocation handler for on the BSP to check and set up

src/cpu/intel/model_1067x/mp_init.c

@@ -94,7 +94,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	southbridge_smm_init();
+	smm_southbridge_enable_smi();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -316,7 +316,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	southbridge_smm_init();
+	smm_southbridge_enable_smi();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -542,7 +542,7 @@ static void post_mp_init(void)
 {
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	southbridge_smm_init();
+	smm_southbridge_enable_smi();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -202,7 +202,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 void smm_initialize(void)
 {
 	/* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
 
 	/*
 	 * Run the relocation handler for on the BSP to check and set up

src/include/cpu/intel/smm_reloc.h

@@ -17,7 +17,6 @@
 #include <types.h>
 
 /* These helpers are for performing SMM relocation. */
-void southbridge_smm_init(void);
 u32 northbridge_get_tseg_base(void);
 u32 northbridge_get_tseg_size(void);
 void northbridge_write_smram(u8 smram);
@@ -25,8 +24,12 @@ void northbridge_write_smram(u8 smram);
 void smm_lock(void);
 void smm_relocate(void);
 
-/* parallel MP helper functions */
+/* The initialization of the southbridge is split into 2 components. One is
-void southbridge_smm_clear_state(void);
+ * for clearing the state in the SMM registers. The other is for enabling
+ * SMIs. They are split so that other work between the 2 actions. */
+void smm_southbridge_clear_state(void);
+void smm_southbridge_enable_smi(void);
+void smm_southbridge_enable(uint16_t pm1_events);
 
 /* To be removed. */
 void smm_initialize(void);

src/soc/intel/apollolake/cpu.c

@@ -31,6 +31,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -39,7 +40,6 @@
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
 #include <intelblocks/sgx.h>
-#include <intelblocks/smm.h>
 #include <reg_script.h>
 #include <romstage_handoff.h>
 #include <soc/cpu.h>

src/soc/intel/baytrail/cpu.c

@@ -17,7 +17,9 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
@@ -25,7 +27,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <reg_script.h>
 
 #include <soc/iosf.h>
@@ -198,10 +199,10 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
 
 void baytrail_init_cpus(struct device *dev)

src/soc/intel/baytrail/gpio.c

@@ -190,7 +190,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 			route_reg |= ROUTE_SCI << (2 * (i + 8));
 		}
 	}
-	southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
+	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
 static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],

src/soc/intel/baytrail/include/soc/smm.h

@@ -16,6 +16,8 @@
 #ifndef _BAYTRAIL_SMM_H_
 #define _BAYTRAIL_SMM_H_
 
+#include <types.h>
+
 /* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
  * is included after chipset code. This causes the chipset's Kconfig to be
  * clobbered by the arch/x86/Kconfig if they have the same name. */
@@ -29,17 +31,12 @@ static inline int smm_region_size(void)
 
 uintptr_t smm_region_start(void);
 
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
-
 enum {
 	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
 	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
 	SMM_SAVE_PARAM_COUNT
 };
 
+void smm_southcluster_save_param(int param, uint32_t data);
+
 #endif /* _BAYTRAIL_SMM_H_ */

src/soc/intel/baytrail/pcie.c

@@ -215,7 +215,7 @@ static void byt_pcie_enable(struct device *dev)
 		strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
 
 		if (config->pcie_wake_enable)
-			southcluster_smm_save_param(
+			smm_southcluster_save_param(
 				SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
 	}
 

src/soc/intel/baytrail/smm.c

@@ -20,6 +20,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
 #include <soc/smm.h>
@@ -27,12 +28,12 @@
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
 
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
 	smm_save_params[param] = data;
 }
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -57,7 +58,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
 	u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
 
 	/* Enable SMI generation:
 	 *  - on APMC writes (io 0xb2)

src/soc/intel/braswell/cpu.c

@@ -18,7 +18,9 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
@@ -26,7 +28,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <reg_script.h>
 #include <soc/iosf.h>
 #include <soc/msr.h>
@@ -217,10 +218,10 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
 
 void soc_init_cpus(struct device *dev)

src/soc/intel/braswell/gpio.c

@@ -176,7 +176,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
 	route_reg, alt_gpio_smi, gpe0a_en);
 #endif
 	/* Save as an smm param */
-	southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
+	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
 

src/soc/intel/braswell/include/soc/smm.h

@@ -17,13 +17,7 @@
 #ifndef _SOC_SMM_H_
 #define _SOC_SMM_H_
 
-
+#include <types.h>
-#if ENV_RAMSTAGE
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
 
 enum {
 	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
@@ -31,4 +25,6 @@ enum {
 	SMM_SAVE_PARAM_COUNT
 };
 
+void smm_southcluster_save_param(int param, uint32_t data);
+
 #endif /* _SOC_SMM_H_ */

src/soc/intel/braswell/pcie.c

@@ -148,7 +148,7 @@ static void pcie_enable(struct device *dev)
 		strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
 
 		if (config->pcie_wake_enable)
-			southcluster_smm_save_param(
+			smm_southcluster_save_param(
 				SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
 	}
 

src/soc/intel/braswell/smm.c

@@ -19,6 +19,7 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/iomap.h>
@@ -28,12 +29,12 @@
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
 
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
 	smm_save_params[param] = data;
 }
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -58,7 +59,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
 	void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
 
 	/*
 	 * Enable SMI generation:

src/soc/intel/broadwell/cpu.c

@@ -24,6 +24,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
@@ -651,7 +652,7 @@ static void post_mp_init(void)
 
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
 
 	/* Lock down the SMRAM space. */
 	smm_lock();

src/soc/intel/broadwell/include/soc/smm.h

@@ -53,22 +53,4 @@ static inline int smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
-/* These helpers are for performing SMM relocation. */
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-
-/* The initialization of the southbridge is split into 2 components. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
-
 #endif

src/soc/intel/broadwell/smi.c

@@ -20,12 +20,13 @@
 #include <arch/io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <soc/iomap.h>
 #include <soc/pch.h>
 #include <soc/pm.h>
 #include <soc/smm.h>
 
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	u32 smi_en;
 
@@ -47,7 +48,7 @@ void southbridge_smm_clear_state(void)
 	clear_gpe_status();
 }
 
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events */
@@ -65,7 +66,7 @@ void southbridge_smm_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
-void southbridge_trigger_smi(void)
+static void __unused southbridge_trigger_smi(void)
 {
 	/**
 	 * There are several methods of raising a controlled SMI# via
@@ -85,7 +86,7 @@ void southbridge_trigger_smi(void)
 	outb(0x00, 0xb2);
 }
 
-void southbridge_clear_smi_status(void)
+static void __unused southbridge_clear_smi_status(void)
 {
 	/* Clear SMI status */
 	clear_smi_status();

src/soc/intel/broadwell/smmrelocate.c

@@ -25,6 +25,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
@@ -287,7 +288,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 void smm_initialize(void)
 {
 	/* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
 
 	/*
 	 * Run the relocation handler for on the BSP to check and set up

src/soc/intel/cannonlake/cpu.c

@@ -19,10 +19,10 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
-#include <intelblocks/smm.h>
 #include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>

src/soc/intel/cannonlake/include/soc/smm.h

@@ -41,13 +41,4 @@ struct smm_relocation_params {
 	int smm_save_state_in_msrs;
 };
 
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
 #endif

src/soc/intel/cannonlake/smmrelocate.c

@@ -27,8 +27,8 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
-#include <intelblocks/smm.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>

src/soc/intel/common/block/include/intelblocks/smm.h

@@ -1,36 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
 
-#ifndef SOC_INTEL_COMMON_BLOCK_SMM_H
-#define SOC_INTEL_COMMON_BLOCK_SMM_H
-
-#include <stdint.h>
-
-/*
- * This common code block relies on each specific SOC defining the macro
- * ENABLE_SMI_PARAMS for the values needed for SMI enabling on the
- * specific SOC
- */
-
-/*
- * The initialization of the southbridge is split into 2 compoments. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs.
- */
-void smm_southbridge_clear_state(void);
-void smm_southbridge_enable(uint16_t pm1_events);
-
-#endif

src/soc/intel/common/block/smm/smm.c

@@ -18,8 +18,8 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <intelblocks/pmclib.h>
-#include <intelblocks/smm.h>
 #include <intelblocks/systemagent.h>
 #include <soc/pm.h>
 

src/soc/intel/denverton_ns/cpu.c

@@ -22,6 +22,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
@@ -254,7 +255,7 @@ static void post_mp_init(void)
 	 * Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
 	 */
-	southcluster_smm_enable_smi();
+	smm_southbridge_enable_smi();
 }
 
 /*
@@ -268,7 +269,7 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = relocation_handler,
 	.post_mp_init = post_mp_init,
 };

src/soc/intel/denverton_ns/include/soc/smm.h

@@ -24,10 +24,4 @@ struct smm_relocation_attrs {
 	uint32_t smrr_mask;
 };
 
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-#endif
-
 #endif /* _DENVERTON_NS_SMM_H_ */

src/soc/intel/denverton_ns/smm.c

@@ -21,13 +21,14 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 
 #include <soc/iomap.h>
 #include <soc/soc_util.h>
 #include <soc/pm.h>
 #include <soc/smm.h>
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -48,7 +49,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");

src/soc/intel/fsp_baytrail/cpu.c

@@ -17,7 +17,9 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/em64t100_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
@@ -25,7 +27,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <reg_script.h>
 
 #include <soc/msr.h>
@@ -152,7 +153,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
 static void enable_smis(void)
 {
 	if (CONFIG(HAVE_SMI_HANDLER))
-		southcluster_smm_enable_smi();
+		smm_southbridge_enable_smi();
 }
 
 static const struct mp_ops mp_ops = {
@@ -160,7 +161,7 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
 	.relocation_handler = relocation_handler,
 	.post_mp_init = enable_smis,
 };

src/soc/intel/fsp_baytrail/gpio.c

@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <soc/gpio.h>
 #include <soc/pmc.h>
-#include <soc/smm.h>
 
 /*
  * GPIO-to-Pad LUTs
@@ -211,7 +210,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 		}
 	}
 
-	southcluster_smm_save_gpio_route(route_reg);
+	smm_southcluster_save_gpio_route(route_reg);
 }
 
 static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],

src/soc/intel/fsp_baytrail/include/soc/gpio.h

@@ -349,6 +349,7 @@ struct gpio_bank {
 	const u8 gpio_f1_range_end;
 };
 
+void smm_southcluster_save_gpio_route(uint32_t route);
 void setup_soc_gpios(struct soc_gpio_config *config);
 /* This function is weak and can be overridden by a mainboard function. */
 struct soc_gpio_config* mainboard_get_gpios(void);

src/soc/intel/fsp_baytrail/include/soc/smm.h

@@ -30,11 +30,4 @@ static inline int smm_region_size(void)
 
 uintptr_t smm_region_start(void);
 
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_gpio_route(uint32_t route);
-#endif
-
 #endif /* _BAYTRAIL_SMM_H_ */

src/soc/intel/fsp_baytrail/smm.c

@@ -20,21 +20,22 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <bootstate.h>
+#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
-#include <soc/smm.h>
 
 /* Save the gpio route register. The settings are committed from
- * southcluster_smm_enable_smi(). */
+ * smm_southbridge_enable_smi(). */
 static uint32_t gpio_route;
 
-void southcluster_smm_save_gpio_route(uint32_t route)
+void smm_southcluster_save_gpio_route(uint32_t route)
 {
 	gpio_route = route;
 }
 
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	uint32_t smi_en;
 
@@ -59,7 +60,7 @@ void southcluster_smm_clear_state(void)
 	clear_pmc_status();
 }
 
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
 	u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -84,7 +85,7 @@ static void southcluster_smm_route_gpios(void)
 	outl(alt_gpio_reg, alt_gpio_smi);
 }
 
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
@@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void)
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
 
 	/* Enable SMI generation:
 	 *  - on APMC writes (io 0xb2)

src/soc/intel/fsp_broadwell_de/cpu.c

@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
@@ -99,7 +100,7 @@ static void post_mp_init(void)
 	set_max_ratio();
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	   start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
 
 	/* Set SMI lock bits. */
 	smm_lock();

src/soc/intel/fsp_broadwell_de/include/soc/smm.h

@@ -54,24 +54,4 @@ static inline int smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
-/* These helpers are for performing SMM relocation. */
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-
-/*
- * The initialization of the southbridge is split into 2 components. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions.
- */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
-
 #endif

src/soc/intel/fsp_broadwell_de/smi.c

@@ -16,12 +16,13 @@
  */
 
 #include <console/console.h>
+#include <cpu/intel/smm_reloc.h>
 #include <arch/io.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/smm.h>
 
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	u32 smi_en;
 
@@ -41,7 +42,9 @@ void southbridge_smm_clear_state(void)
 	clear_pm1_status();
 }
 
-void southbridge_smm_enable_smi(void)
+static void southbridge_clear_smi_status(void);
+
+void smm_southbridge_enable_smi(void)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 
@@ -54,7 +57,7 @@ void southbridge_smm_enable_smi(void)
 	enable_smi(EOS | GBL_SMI_EN);
 }
 
-void southbridge_trigger_smi(void)
+static void  __unused southbridge_trigger_smi(void)
 {
 	/*
 	 * There are several methods of raising a controlled SMI# via
@@ -74,7 +77,7 @@ void southbridge_trigger_smi(void)
 	outb(0x00, 0xb2);
 }
 
-void southbridge_clear_smi_status(void)
+static void southbridge_clear_smi_status(void)
 {
 	/* Clear SMI status */
 	clear_smi_status();

src/soc/intel/fsp_broadwell_de/smmrelocate.c

@@ -24,6 +24,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <soc/lpc.h>
@@ -296,7 +297,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 void smm_initialize(void)
 {
 	/* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
 
 	/* Run the relocation handler for on the BSP to check and set up
 	   parallel SMM relocation. */

src/soc/intel/icelake/cpu.c

@@ -19,12 +19,12 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <fsp/api.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/msr.h>
-#include <intelblocks/smm.h>
 #include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>

src/soc/intel/icelake/include/soc/smm.h

@@ -40,12 +40,4 @@ struct smm_relocation_params {
 	int smm_save_state_in_msrs;
 };
 
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
 #endif

src/soc/intel/icelake/smmrelocate.c

@@ -26,8 +26,8 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
-#include <intelblocks/smm.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>

src/soc/intel/skylake/cpu.c

@@ -31,11 +31,11 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <cpu/x86/smm.h>
+#include <cpu/intel/smm_reloc.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/sgx.h>
-#include <intelblocks/smm.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>

src/soc/intel/skylake/include/soc/smm.h

@@ -42,12 +42,4 @@ struct smm_relocation_params {
 	int smm_save_state_in_msrs;
 };
 
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
 #endif

src/soc/intel/skylake/smmrelocate.c

@@ -26,8 +26,8 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
-#include <intelblocks/smm.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>

src/southbridge/intel/common/smi.c

@@ -34,7 +34,7 @@ u16 get_pmbase(void)
 	return lpc_get_pmbase();
 }
 
-void southbridge_smm_init(void)
+void smm_southbridge_enable_smi(void)
 {
 	u32 smi_en;
 	u16 pm1_en;
@@ -123,7 +123,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 	);
 }
 
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	u32 smi_en;
 

src/southbridge/intel/lynxpoint/pch.h

@@ -183,14 +183,6 @@ void pch_log_state(void);
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 
-/* These helpers are for performing SMM relocation. */
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-/* The initialization of the southbridge is split into 2 compoments. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
 #else
 void enable_smbus(void);
 void enable_usb_bar(void);

src/southbridge/intel/lynxpoint/smi.c

@@ -19,12 +19,13 @@
 #include <device/pci.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
 #include "pch.h"
 
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
 	u32 smi_en;
 
@@ -50,7 +51,7 @@ void southbridge_smm_clear_state(void)
 	clear_gpe_status();
 }
 
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events */
@@ -68,7 +69,7 @@ void southbridge_smm_enable_smi(void)
 	enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
 }
 
-void southbridge_trigger_smi(void)
+static void  __unused southbridge_trigger_smi(void)
 {
 	/**
 	 * There are several methods of raising a controlled SMI# via
@@ -88,7 +89,7 @@ void southbridge_trigger_smi(void)
 	outb(0x00, 0xb2);
 }
 
-void southbridge_clear_smi_status(void)
+static void __unused southbridge_clear_smi_status(void)
 {
 	/* Clear SMI status */
 	clear_smi_status();