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baytrail: gpio: Add support for direct / dedicated IRQs

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Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
IRQs for both SCORE and SSUS banks.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.

Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
Reviewed-on: https://chromium-review.googlesource.com/176165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4962
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Shawn Nematbakhsh
2013-11-08 16:43:34 -08:00
committed by Aaron Durbin
parent 7e9634ffc0
commit fb494d68ff
3 changed files with 97 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/soc/intel/baytrail/gpio.c
View File

@@ -179,6 +179,25 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
southcluster_smm_save_gpio_route(route_reg);
}
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
u32 val;
int i;
/* Write all four DIRQ registers */
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
write32(reg + i * 4, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
reg + i * 4, val);
#endif
}
}
void setup_soc_gpios(struct soc_gpio_config *config)
{
if (config) {
@@ -186,7 +205,13 @@ void setup_soc_gpios(struct soc_gpio_config *config)
setup_gpios(config->score, &gpscore_bank);
setup_gpios(config->ssus, &gpssus_bank);
setup_gpio_route(config->ssus, config->score);
if (config->core_dirq)
setup_dirqs(*config->core_dirq, &gpscore_bank);
if (config->sus_dirq)
setup_dirqs(*config->sus_dirq, &gpssus_bank);
}
}
struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)