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intel/fsp: Add post codes for FSP phases

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Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.

This will make it more consistent to debug FSP hangs and resets.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell

Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie
2015-11-22 14:53:57 -08:00
committed by Patrick Georgi
parent 590ac64d55
commit fb50983008
8 changed files with 58 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/fsp1_0/cache_as_ram.inc
View File

@@ -47,7 +47,7 @@ find_fsp_ret:
jmp .Lhlt
find_fsp_ok:
post_code(0x22)
post_code(POST_FSP_TEMP_RAM_INIT)
/* Calculate entry into FSP */
mov 0x30(%ebp), %eax /* Load TempRamInitEntry */

3
src/drivers/intel/fsp1_0/fsp_util.c
View File

@@ -92,6 +92,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
/* Call back to romstage for board specific changes */
romstage_fsp_rt_buffer_callback(&FspRtBuffer);
post_code(POST_FSP_MEMORY_INIT);
FspInitApi(&FspInitParams);
/* Should never return. Control will continue from ContinuationFunc */
@@ -321,6 +322,7 @@ static void fsp_after_pci_enum(void *unused)
{
/* This call needs to be done before resource allocation. */
printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
FspNotify(EnumInitPhaseAfterPciEnumeration);
printk(BIOS_DEBUG,
"Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
@@ -334,6 +336,7 @@ static void fsp_finalize(void *unused)
{
printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
print_fsp_info();
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
FspNotify(EnumInitPhaseReadyToBoot);
printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
}

2
src/drivers/intel/fsp1_1/after_raminit.S
View File

@@ -31,6 +31,8 @@
/* Switch to the stack in RAM */
movl %eax, %esp
post_code(POST_FSP_TEMP_RAM_EXIT)
/* Calculate TempRamExit entry into FSP */
movl fih_car, %ebp
mov 0x40(%ebp), %eax

2
src/drivers/intel/fsp1_1/cache_as_ram.inc
View File

@@ -65,7 +65,7 @@ find_fsp_ret:
cmp $CONFIG_FSP_LOC, %eax
jbe halt1
post_code(0x22)
post_code(POST_FSP_TEMP_RAM_INIT)
/* Calculate entry into FSP */
mov 0x30(%ebp), %eax /* Load TempRamInitEntry */

9
src/drivers/intel/fsp1_1/fsp_util.c
View File

@@ -161,8 +161,13 @@ void fsp_notify(u32 phase)
fsp_header_ptr->NotifyPhaseEntryOffset);
notify_phase_params.Phase = phase;
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
if (phase == EnumInitPhaseReadyToBoot) {
timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
} else {
timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
status = notify_phase_proc(&notify_phase_params);

1
src/drivers/intel/fsp1_1/raminit.c
View File

@@ -122,6 +122,7 @@ void raminit(struct romstage_params *params)
fsp_memory_init_params.HobListPtr);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
post_code(POST_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
post_code(0x37);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);

1
src/drivers/intel/fsp1_1/ramstage.c
View File

@@ -137,6 +137,7 @@ static void fsp_run_silicon_init(int is_s3_wakeup)
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
&silicon_init_params, fsp_silicon_init);
post_code(POST_FSP_SILICON_INIT);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);