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util/inteltool: Add support for Alderlake P in inteltool

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TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P

Document number: 626817, 630094, 655258

Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kacper Stojek
2022-08-17 10:28:20 +02:00
committed by Martin Roth
parent f7e52a7aa4
commit fb9110b9e4
6 changed files with 644 additions and 1 deletions
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8
util/inteltool/gpio_groups.c
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@ -20,6 +20,7 @@
#include "gpio_names/sunrise.h"
#include "gpio_names/tigerlake.h"
#include "gpio_names/alderlake_h.h"
#include "gpio_names/alderlake_p.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
@ -217,6 +218,13 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
*community_count = ARRAY_SIZE(alderlake_pch_h_communities);
*pad_stepping = 16;
return alderlake_pch_h_communities;
case PCI_DEVICE_ID_INTEL_ADL_P:
case PCI_DEVICE_ID_INTEL_ADL_M:
case PCI_DEVICE_ID_INTEL_RPL_P:
*community_count = ARRAY_SIZE(alderlake_pch_p_communities);
*pad_stepping = 16;
return alderlake_pch_p_communities;
default:
return NULL;
}