From fbf0bd5b7e5709d2e75e736c39048cd6793665ad Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 24 Aug 2020 14:49:06 -0600 Subject: [PATCH] soc/intel/cannonlake: Allow setting of PCIe subsystem IDs after FSP SiliconInit Change-Id: Ie5c7d497e4a64a2f5e2960a2cdca8e5780dc07ea --- src/soc/intel/cannonlake/fsp_params.c | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 7fb695ba98..d6e874e51a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -646,6 +646,53 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; + + /* Disable setting subsystem ID, which causes it to lock */ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t reserved1:4; + uint64_t segment:16; + uint64_t reserved2:16; + }; + uint64_t segbusdevfuncregister; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t reserved; + }; + const struct svid_ssid_init_entry ssid_table[] = {{{}, {}, }, }; + params->SiSsidTablePtr = (uintptr_t)ssid_table; + params->SiNumberOfSsidTableEntry = 1; + + uint16_t svid = CONFIG_SUBSYSTEM_VENDOR_ID; + uint16_t sdid = CONFIG_SUBSYSTEM_DEVICE_ID; + + /* Program XHCI SSID/SVID before FSP silicon init */ + dev = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!svid || !sdid) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((sdid & 0xffff) << 16) | (svid & 0xffff)); + } + + /* Program HDAudio SSID/SVID before FSP silicon init */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!svid || !sdid) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((sdid & 0xffff) << 16) | (svid & 0xffff)); + } } /* Mainboard GPIO Configuration */