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rpl: Switch to S0iX

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Change-Id: I2ae9d42d422fec32b9a7431ab44e7c7f4073a5da
This commit is contained in:
Jeremy Soller
2023-02-22 13:33:18 -07:00
parent 9f0029c407
commit fc165748a0
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/system76/rpl/Kconfig
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@@ -6,7 +6,6 @@ config BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC select EC_SYSTEM76_EC
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT select INTEL_GMA_HAVE_VBT
@@ -14,7 +13,6 @@ config BOARD_SYSTEM76_RPL_COMMON
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO select NO_UART_ON_SUPERIO
select SOC_INTEL_ALDERLAKE_S3
select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4

2
src/mainboard/system76/rpl/devicetree.cb
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@@ -11,6 +11,8 @@ chip soc/intel/alderlake
# Enable Enhanced Intel SpeedStep # Enable Enhanced Intel SpeedStep
register "eist_enable" = "1" register "eist_enable" = "1"
register "s0ix_enable" = "1"
# Enable C6 DRAM # Enable C6 DRAM
register "enable_c6dram" = "1" register "enable_c6dram" = "1"