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src: Change bare 'unsigned' to 'unsigned int'

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This fixes all of the current code in coreboot/src where a bare
unsigned is used incorrectly. A follow-on will fix the comments
so that we can enable the unsigned lint checker for src/coreboot.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth
2020-11-11 09:18:36 -07:00
committed by Patrick Georgi
parent c6b77d5bf6
commit fc2047b1f7
2 changed files with 51 additions and 51 deletions
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30
src/include/device/dram/ddr2.h
View File

@@ -47,35 +47,35 @@ union dimm_flags_ddr2_st {
* We do not care how these bits are ordered */ * We do not care how these bits are ordered */
struct { struct {
/* Module can work at 5.00V */ /* Module can work at 5.00V */
unsigned operable_5_00V:1; unsigned int operable_5_00V:1;
/* Module can work at 3.33V */ /* Module can work at 3.33V */
unsigned operable_3_33V:1; unsigned int operable_3_33V:1;
/* Module can work at 2.50V */ /* Module can work at 2.50V */
unsigned operable_2_50V:1; unsigned int operable_2_50V:1;
/* Module can work at 1.80V - All DIMMS must be 1.8V operable */ /* Module can work at 1.80V - All DIMMS must be 1.8V operable */
unsigned operable_1_80V:1; unsigned int operable_1_80V:1;
/* Module can work at 1.50V */ /* Module can work at 1.50V */
unsigned operable_1_50V:1; unsigned int operable_1_50V:1;
/* Module can work at 1.35V */ /* Module can work at 1.35V */
unsigned operable_1_35V:1; unsigned int operable_1_35V:1;
/* Module can work at 1.20V */ /* Module can work at 1.20V */
unsigned operable_1_25V:1; unsigned int operable_1_25V:1;
/* Has an 8-bit bus extension, meaning the DIMM supports ECC */ /* Has an 8-bit bus extension, meaning the DIMM supports ECC */
unsigned is_ecc:1; unsigned int is_ecc:1;
/* Supports weak driver */ /* Supports weak driver */
unsigned weak_driver:1; unsigned int weak_driver:1;
/* Supports terminating at 50 Ohm */ /* Supports terminating at 50 Ohm */
unsigned terminate_50ohms:1; unsigned int terminate_50ohms:1;
/* Partial Array Self Refresh */ /* Partial Array Self Refresh */
unsigned pasr:1; unsigned int pasr:1;
/* Supports burst length 8 */ /* Supports burst length 8 */
unsigned bl8:1; unsigned int bl8:1;
/* Supports burst length 4 */ /* Supports burst length 4 */
unsigned bl4:1; unsigned int bl4:1;
/* DIMM Package is stack */ /* DIMM Package is stack */
unsigned stacked:1; unsigned int stacked:1;
/* the assembly supports self refresh */ /* the assembly supports self refresh */
unsigned self_refresh:1; unsigned int self_refresh:1;
}; };
unsigned int raw; unsigned int raw;
}; };

72
src/soc/rockchip/rk3399/include/soc/sdram.h
View File

@@ -27,66 +27,66 @@ struct rk3399_ddr_pi_regs {
union noc_ddrtiminga0 { union noc_ddrtiminga0 {
u32 d32; u32 d32;
struct { struct {
unsigned acttoact : 6; unsigned int acttoact : 6;
unsigned reserved0 : 2; unsigned int reserved0 : 2;
unsigned rdtomiss : 6; unsigned int rdtomiss : 6;
unsigned reserved1 : 2; unsigned int reserved1 : 2;
unsigned wrtomiss : 6; unsigned int wrtomiss : 6;
unsigned reserved2 : 2; unsigned int reserved2 : 2;
unsigned readlatency : 8; unsigned int readlatency : 8;
} b; } b;
}; };
union noc_ddrtimingb0 { union noc_ddrtimingb0 {
u32 d32; u32 d32;
struct { struct {
unsigned rdtowr : 5; unsigned int rdtowr : 5;
unsigned reserved0 : 3; unsigned int reserved0 : 3;
unsigned wrtord : 5; unsigned int wrtord : 5;
unsigned reserved1 : 3; unsigned int reserved1 : 3;
unsigned rrd : 4; unsigned int rrd : 4;
unsigned reserved2 : 4; unsigned int reserved2 : 4;
unsigned faw : 6; unsigned int faw : 6;
unsigned reserved3 : 2; unsigned int reserved3 : 2;
} b; } b;
}; };
union noc_ddrtimingc0 { union noc_ddrtimingc0 {
u32 d32; u32 d32;
struct { struct {
unsigned burstpenalty : 4; unsigned int burstpenalty : 4;
unsigned reserved0 : 4; unsigned int reserved0 : 4;
unsigned wrtomwr : 6; unsigned int wrtomwr : 6;
unsigned reserved1 : 18; unsigned int reserved1 : 18;
} b; } b;
}; };
union noc_devtodev0 { union noc_devtodev0 {
u32 d32; u32 d32;
struct { struct {
unsigned busrdtord : 3; unsigned int busrdtord : 3;
unsigned reserved0 : 1; unsigned int reserved0 : 1;
unsigned busrdtowr : 3; unsigned int busrdtowr : 3;
unsigned reserved1 : 1; unsigned int reserved1 : 1;
unsigned buswrtord : 3; unsigned int buswrtord : 3;
unsigned reserved2 : 1; unsigned int reserved2 : 1;
unsigned buswrtowr : 3; unsigned int buswrtowr : 3;
unsigned reserved3 : 17; unsigned int reserved3 : 17;
} b; } b;
}; };
union noc_ddrmode { union noc_ddrmode {
u32 d32; u32 d32;
struct { struct {
unsigned autoprecharge : 1; unsigned int autoprecharge : 1;
unsigned bypassfiltering : 1; unsigned int bypassfiltering : 1;
unsigned fawbank : 1; unsigned int fawbank : 1;
unsigned burstsize : 2; unsigned int burstsize : 2;
unsigned mwrsize : 2; unsigned int mwrsize : 2;
unsigned reserved2 : 1; unsigned int reserved2 : 1;
unsigned forceorder : 8; unsigned int forceorder : 8;
unsigned forceorderstate : 8; unsigned int forceorderstate : 8;
unsigned reserved3 : 8; unsigned int reserved3 : 8;
} b; } b;
}; };