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soc/intel/*: Move prmrr_core_configure

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Move prmrr_core_configure before clearing MCEs.

This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.

According to Document 565432 this should be no issue in regards to
SGX activation.

Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph
2021-01-25 10:46:16 +01:00
committed by Patrick Georgi
parent aacbd66a85
commit fc36e9fb0e
2 changed files with 8 additions and 8 deletions
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8
src/soc/intel/apollolake/cpu.c
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@ -48,6 +48,10 @@ static const struct reg_script core_msr_script[] = {
void soc_core_init(struct device *cpu)
{
/* Configure Core PRMRR for SGX. */
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
prmrr_core_configure();
/* Clear out pending MCEs */
/* TODO(adurbin): Some of these banks are core vs package
scope. For now every CPU clears every bank. */
@ -66,10 +70,6 @@ void soc_core_init(struct device *cpu)
*/
enable_pm_timer_emulation();
/* Configure Core PRMRR for SGX. */
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
prmrr_core_configure();
/* Set Max Non-Turbo ratio if RAPL is disabled. */
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
cpu_set_p_state_to_max_non_turbo_ratio();