Add Board Checklist Support

Build the <board>_checklist.html file which contains a checklist table
for each stage of coreboot.  This processing builds a set of implemented
(done) routines which are marked green in the table.  The remaining
required routines (work-to-do) are marked red in the table and the
optional routines are marked yellow in the table.  The table heading
for each stage contains a completion percentage in terms of count of
routines (done .vs. required).

Add some Kconfig values:
*  CREATE_BOARD_CHECKLIST - When selected creates the checklist file
*  MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the
   Documenation directory
*  CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files:
   *  <stage>_complete.dat - Lists all of the weak routines
   *  <stage>_optional.dat - Lists weak routines which may be optionally
      implemented

TEST=Build with Galileo Gen2.

Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat

@@ -0,0 +1,77 @@
+arch_segment_loaded
+backup_top_of_ram
+bootblock_mainboard_early_init
+bootblock_mainboard_init
+bootblock_soc_early_init
+bootblock_soc_init
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fill_power_state
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_memory_init_params
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+mrc_cache_get_current
+mrc_cache_stash_data
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+raminit
+ramstage_cache_invalid
+report_memory_config
+save_chromeos_gpios
+setup_stack_and_mtrrs
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_ram_init
+soc_after_silicon_init
+soc_display_memory_init_params
+soc_display_silicon_init_params
+soc_fill_acpi_wake
+soc_memory_init_params
+soc_pre_ram_init
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+timestamp_tick_freq_mhz
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init
+wifi_regulatory_domain
+write_smp_table

src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat

@@ -0,0 +1,53 @@
+acpi_create_serialio_ssdt
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_io_trap_handler
+mainboard_post
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_silicon_init
+soc_display_silicon_init_params
+soc_fill_acpi_wake
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+timestamp_tick_freq_mhz
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+wifi_regulatory_domain
+write_smp_table

src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat

@@ -0,0 +1,46 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fw_cfg_acpi_tables
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+lb_board
+lb_framebuffer
+mainboard_add_dimm_info
+mainboard_io_trap_handler
+mainboard_post
+mainboard_silicon_init_params
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+mainboard_suspend_resume
+map_oprom_vendev
+mirror_payload
+northbridge_smi_handler
+nvm_mmio_to_flash_offset
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+smbios_mainboard_bios_version
+smbios_mainboard_manufacturer
+smbios_mainboard_product_name
+smbios_mainboard_serial_number
+smbios_mainboard_set_uuid
+smbios_mainboard_version
+smm_disable_busmaster
+soc_after_silicon_init
+soc_display_silicon_init_params
+soc_silicon_init_params
+soc_skip_ucode_update
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+wifi_regulatory_domain
+write_smp_table

src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat

@@ -0,0 +1,54 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+fill_power_state
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+init_timer
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_fill_spd_data
+mainboard_io_trap_handler
+mainboard_memory_init_params
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+migrate_power_state
+mrc_cache_get_current_with_version
+mrc_cache_stash_data_with_version
+platform_prog_run
+platform_segment_loaded
+print_fsp_info
+raminit
+ramstage_cache_invalid
+report_memory_config
+romstage_common
+save_chromeos_gpios
+set_max_freq
+setup_stack_and_mtrrs
+smm_region
+smm_region_size
+soc_after_ram_init
+soc_display_memory_init_params
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+soc_memory_init_params
+soc_pre_ram_init
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot

src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat

@@ -0,0 +1,34 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+get_sw_write_protect_state
+get_top_of_ram
+gpio_acpi_path
+mainboard_add_dimm_info
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_post
+mainboard_romstage_entry
+mainboard_save_dimm_info
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+soc_after_ram_init
+soc_display_memory_init_params
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+soc_memory_init_params
+soc_pre_ram_init
+southbridge_smi_handler
+stage_cache_add
+stage_cache_load_stage
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init

src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat

@@ -0,0 +1,35 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+cbfs_master_header_locator
+cbmem_fail_resume
+clear_recovery_mode_switch
+cpu_smi_handler
+get_sw_write_protect_state
+gpio_acpi_path
+init_timer
+mainboard_check_ec_image
+mainboard_io_trap_handler
+mainboard_post
+mainboard_smi_apmc
+mainboard_smi_gpi
+mainboard_smi_sleep
+map_oprom_vendev
+platform_prog_run
+platform_segment_loaded
+save_chromeos_gpios
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init

src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat

@@ -0,0 +1,22 @@
+arch_segment_loaded
+backup_top_of_ram
+boot_device_init
+car_mainboard_post_console_init
+car_mainboard_pre_console_init
+car_soc_post_console_init
+car_soc_pre_console_init
+mainboard_check_ec_image
+mainboard_post
+platform_prog_run
+platform_segment_loaded
+soc_display_mtrrs
+soc_get_variable_mtrr_count
+stage_cache_add
+stage_cache_load_stage
+timestamp_get
+tsc_freq_mhz
+vb2ex_hwcrypto_digest_extend
+vb2ex_hwcrypto_digest_finalize
+vb2ex_hwcrypto_digest_init
+vboot_platform_prepare_reboot
+verstage_mainboard_init