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cpu/x86/lapic: Support x86_64 and clean up code

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Most LAPIC registers are 32bit, and thus the use of long is valid on
x86_32, however it doesn't work on x86_64.

* Don't use long as it is 64bit on x86_64, which breaks interrupts
  in QEMU and thus SeaBIOS wouldn't time out the boot menu
* Get rid of unused defines
* Get rid of unused atomic xchg code

Tested on QEMU Q35 with x86_64 enabled: Interrupts work again.
Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working.
Tested on Lenovo T410 with x86_64 enabled.

Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
2019-11-12 16:30:14 +01:00
committed by Patrick Georgi
parent 6f1d35e72d
commit fc57d6c4c2
5 changed files with 22 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/model_2065x/model_2065x_init.c
View File

@@ -228,7 +228,7 @@ static void model_2065x_init(struct device *cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid(),
printk(BIOS_INFO, "CPU:lapic=%d, boot_cpu=%d\n", lapicid(),
boot_cpu());
/* Setup Page Attribute Tables (PAT) */

2
src/cpu/x86/lapic/lapic.c
View File

@@ -47,6 +47,6 @@ void do_lapic_init(void)
LAPIC_DELIVERY_MODE_NMI)
);
printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid());
printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid());
printk(BIOS_INFO, "done.\n");
}

8
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -91,7 +91,7 @@ static void recover_lowest_1M(void)
static int lapic_start_cpu(unsigned long apicid)
{
int timeout;
unsigned long send_status, accept_status;
uint32_t send_status, accept_status;
int j, maxlvt;
/*
@@ -123,11 +123,11 @@ static int lapic_start_cpu(unsigned long apicid)
printk(BIOS_ERR, "CPU %ld: First APIC write timed out. "
"Disabling\n", apicid);
// too bad.
printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk(BIOS_ERR, "Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
printk(BIOS_ERR, "ESR is 0x%lx\n",
printk(BIOS_ERR, "ESR is 0x%x\n",
lapic_read(LAPIC_ESR));
}
return 0;
@@ -216,7 +216,7 @@ static int lapic_start_cpu(unsigned long apicid)
if (send_status)
printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)
printk(BIOS_WARNING, "APIC delivery error (%lx).\n",
printk(BIOS_WARNING, "APIC delivery error (%x).\n",
accept_status);
if (send_status || accept_status)
return 0;