mb/system76/mtl: Add Lemur Pro 13

The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.

There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.

Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Jeremy Soller 2024-08-28 08:24:34 -06:00 committed by Tim Crawford
parent c4a2c09655
commit fcb9a0ff05
No known key found for this signature in database
GPG Key ID: 68E558D2BBD856E3
15 changed files with 1672 additions and 0 deletions

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@ -37,6 +37,20 @@ config BOARD_SYSTEM76_DARP10_B
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_METEORLAKE_U_H
config BOARD_SYSTEM76_LEMP13
select BOARD_SYSTEM76_MTL_COMMON
select DRIVERS_I2C_TAS5825M
select HAVE_SPD_IN_CBFS
select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_SYSTEM76_LEMP13_B
select BOARD_SYSTEM76_MTL_COMMON
select DRIVERS_I2C_TAS5825M
select HAVE_SPD_IN_CBFS
select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
if BOARD_SYSTEM76_MTL_COMMON if BOARD_SYSTEM76_MTL_COMMON
config MAINBOARD_DIR config MAINBOARD_DIR
@ -44,6 +58,7 @@ config MAINBOARD_DIR
config VARIANT_DIR config VARIANT_DIR
default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
config OVERRIDE_DEVICETREE config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@ -51,13 +66,18 @@ config OVERRIDE_DEVICETREE
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10" if BOARD_SYSTEM76_DARP10
default "darp10-b" if BOARD_SYSTEM76_DARP10_B default "darp10-b" if BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13
default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
config MAINBOARD_SMBIOS_PRODUCT_NAME config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
config MAINBOARD_VERSION config MAINBOARD_VERSION
default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10" if BOARD_SYSTEM76_DARP10
default "darp10-b" if BOARD_SYSTEM76_DARP10_B default "darp10-b" if BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13
default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
config CMOS_DEFAULT_FILE config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"

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@ -5,3 +5,9 @@ config BOARD_SYSTEM76_DARP10
config BOARD_SYSTEM76_DARP10_B config BOARD_SYSTEM76_DARP10_B
bool "darp10-b" bool "darp10-b"
config BOARD_SYSTEM76_LEMP13
bool "lemp13"
config BOARD_SYSTEM76_LEMP13_B
bool "lemp13-b"

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@ -12,3 +12,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/ramstage.c ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD samsung-M425R1GB4PB0-CWMOD

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@ -0,0 +1,65 @@
# Samsung M425R1GB4BB0-CQKOD
30 10 12 03 04 00 40 42 00 00 00 00 90 02 00 00
00 00 00 00 A0 01 F2 03 7A 0D 00 00 00 00 80 3E
80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
27 10 1A 41 28 10 27 10 C4 09 04 4C 1D 0C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 D1
80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
42 34 42 42 30 2D 43 51 4B 4F 44 20 20 20 20 20
20 20 20 20 20 20 20 00 80 CE 95 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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@ -0,0 +1,65 @@
# Samsung M425R1GB4PB0-CWMOD
30 10 12 03 04 00 40 42 00 00 00 00 B0 02 09 00
00 00 00 00 65 01 F2 03 7A AD 00 00 00 00 80 3E
80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
27 10 CD 37 28 10 27 10 C4 09 04 4C 1D 0C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 5E 9B
80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
42 34 50 42 30 2D 43 57 4D 4F 44 20 20 20 20 20
20 20 20 20 20 20 20 00 80 CE 50 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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@ -0,0 +1,12 @@
FLASH 32M {
SI_DESC 16K
SI_ME 10128K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,2 @@
Board name: lemp13
Release year: 2024

Binary file not shown.

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@ -0,0 +1,208 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A07, NONE),
PAD_NC(GPP_A08, NONE),
PAD_NC(GPP_A09, NONE),
PAD_NC(GPP_A10, NONE),
PAD_CFG_GPO(GPP_A11, 0, PLTRST),
PAD_NC(GPP_A12, NONE),
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A14, 0, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A15, 0, UP_20K, PLTRST),
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_TERM_GPO(GPP_A18, 0, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_A20, 0, NATIVE, DEEP),
PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
_PAD_CFG_STRUCT(GPP_B00, 0x40100100, 0x0000),
PAD_CFG_GPO(GPP_B01, 0, PLTRST),
PAD_CFG_GPO(GPP_B02, 0, PLTRST),
PAD_CFG_GPO(GPP_B03, 0, PLTRST),
PAD_CFG_GPO(GPP_B04, 0, PLTRST),
PAD_CFG_GPO(GPP_B05, 1, PLTRST),
PAD_CFG_GPO(GPP_B06, 0, DEEP),
PAD_CFG_GPO(GPP_B07, 1, DEEP),
PAD_CFG_GPO(GPP_B08, 1, DEEP),
PAD_CFG_GPI(GPP_B09, NONE, DEEP),
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // CPU_HDMI_HPD
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
PAD_CFG_GPO(GPP_B17, 1, PLTRST), // HDMI_EN
PAD_CFG_GPO(GPP_B18, 1, PLTRST),
PAD_CFG_GPO(GPP_B19, 1, PLTRST),
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
PAD_CFG_GPO(GPP_B21, 0, PLTRST),
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
PAD_CFG_GPO(GPP_B23, 1, DEEP),
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA_DDR
PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // GPP_C2_STRAP
PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // GPP_C5_STRAP
PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // TBT_I2C_SCL
PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // TBT_I2C_SDA
PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), // GPP_C08_TEST
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // CARD_CLKREQ
PAD_CFG_GPO(GPP_C10, 0, PLTRST), // 5G_PCIE_CLKREQ
PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // WLAN_CLKREQ
PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // GPP_C13-TEST (typo from schematic)
PAD_CFG_GPO(GPP_C13, 1, DEEP),
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), // GPP_C15
// GPP_C16 (TBTA_LSX0_TXD) configured by FSP
// GPP_C17 (TBTA_LSX0_RXD) configured by FSP
// GPP_C18 not connected
// GPP_C19 not connected
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
// GPP_C22 not connected
// GPP_C23 not connected
PAD_CFG_GPO(GPP_D00, 1, PLTRST),
PAD_CFG_GPO(GPP_D01, 1, PLTRST),
PAD_CFG_GPO(GPP_D02, 1, PLTRST),
PAD_NC(GPP_D03, NONE),
PAD_CFG_GPO(GPP_D04, 0, PLTRST),
PAD_CFG_GPO(GPP_D05, 1, PLTRST),
PAD_CFG_GPO(GPP_D06, 0, PLTRST),
PAD_CFG_GPO(GPP_D07, 0, PLTRST),
PAD_CFG_GPO(GPP_D08, 0, PLTRST),
PAD_CFG_GPO(GPP_D09, 0, PLTRST),
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
PAD_CFG_GPO(GPP_D14, 0, PLTRST),
PAD_CFG_GPO(GPP_D15, 0, PLTRST),
PAD_CFG_GPO(GPP_D16, 0, DEEP),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
PAD_NC(GPP_D18, NONE), // GPP_D18-TEST
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // SSD2_CLKREQ
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SSD1_CLKREQ
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
PAD_CFG_GPO(GPP_E00, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x1000),
PAD_CFG_GPI(GPP_E02, NONE, DEEP),
PAD_NC(GPP_E03, NONE),
PAD_CFG_GPO(GPP_E04, 0, PLTRST),
PAD_CFG_GPO(GPP_E05, 0, PLTRST),
PAD_CFG_GPI(GPP_E06, NONE, DEEP),
PAD_CFG_GPO(GPP_E07, 0, PLTRST),
PAD_CFG_GPO(GPP_E08, 0, PLTRST),
PAD_CFG_GPI(GPP_E09, NONE, DEEP),
PAD_CFG_GPO(GPP_E10, 0, PLTRST),
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
_PAD_CFG_STRUCT(GPP_E12, 0x84002200, 0x0000),
_PAD_CFG_STRUCT(GPP_E13, 0x44002100, 0x0000),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_E15, 0, PLTRST),
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
PAD_CFG_GPO(GPP_E17, 0, PLTRST),
PAD_NC(GPP_E18, NONE),
PAD_NC(GPP_E19, NONE),
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_CFG_TERM_GPO(GPP_E22, 0, DN_20K, PLTRST),
PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F07, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F08, DN_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_F09, NONE, DEEP),
PAD_NC(GPP_F10, NONE),
PAD_CFG_GPO(GPP_F11, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // AMP_SMB_CLK
_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // AMP_SMB_DATA
PAD_CFG_GPO(GPP_F14, 0, PLTRST),
PAD_CFG_GPO(GPP_F15, 0, PLTRST),
PAD_CFG_GPO(GPP_F16, 0, PLTRST),
PAD_CFG_GPO(GPP_F17, 0, PLTRST),
PAD_CFG_GPO(GPP_F18, 0, DEEP),
PAD_CFG_GPO(GPP_F19, 0, PLTRST),
PAD_CFG_GPO(GPP_F20, 0, PLTRST),
PAD_CFG_GPO(GPP_F21, 0, PLTRST),
PAD_CFG_GPO(GPP_F22, 0, PLTRST),
PAD_CFG_GPO(GPP_F23, 0, PLTRST),
PAD_CFG_GPO(GPP_H00, 0, PLTRST),
PAD_CFG_GPO(GPP_H01, 0, PLTRST),
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
PAD_NC(GPP_H03, NONE),
PAD_NC(GPP_H04, NONE),
PAD_NC(GPP_H05, NONE),
PAD_NC(GPP_H06, NONE),
PAD_NC(GPP_H07, NONE),
PAD_NC(GPP_H08, NONE),
PAD_NC(GPP_H09, NONE),
PAD_CFG_GPO(GPP_H10, 0, PLTRST),
PAD_CFG_GPO(GPP_H11, 0, PLTRST),
PAD_NC(GPP_H12, NONE),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_H14, 0, PLTRST),
PAD_CFG_GPO(GPP_H15, 0, PLTRST),
PAD_CFG_GPO(GPP_H16, 0, PLTRST),
PAD_CFG_GPO(GPP_H17, 0, PLTRST),
PAD_NC(GPP_H18, NONE),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_S00, 0, PLTRST),
PAD_CFG_GPO(GPP_S01, 0, PLTRST),
PAD_CFG_GPO(GPP_S02, 0, PLTRST),
PAD_CFG_GPO(GPP_S03, 0, PLTRST),
PAD_CFG_GPO(GPP_S04, 0, PLTRST),
PAD_CFG_GPO(GPP_S05, 0, PLTRST),
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1),
PAD_CFG_GPI(GPP_V07, NATIVE, DEEP),
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
PAD_NC(GPP_V12, NONE),
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V15, NONE, PLTRST, NF1),
PAD_CFG_GPO(GPP_V16, 0, PLTRST),
PAD_CFG_GPO(GPP_V17, 0, PLTRST),
PAD_NC(GPP_V18, NONE),
PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),
PAD_NC(GPP_V20, NONE),
PAD_NC(GPP_V21, NONE),
PAD_NC(GPP_V22, NONE),
PAD_NC(GPP_V23, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC245 */
0x10ec0245, /* Vendor ID */
0x15582624, /* Subsystem ID */
34, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x15582624),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
0x0205004a, 0x02042010, 0x02050038, 0x02046909,
0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
0x05450000, 0x05442000, 0x0545001d, 0x05440800,
0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
0x02050010, 0x02040020, 0x02050010, 0x02040020,
0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
0x02050003, 0x02040002, 0x02050069, 0x02040000,
0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
0x02050010, 0x02040020, 0x02050010, 0x02040020,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/meteorlake
#TODO: POWER LIMITS
#register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
# .tdp_pl1_override = 15,
# .tdp_pl2_override = 46,
#}"
device domain 0 on
subsystemid 0x1558 0x2624 inherit
device ref tbt_pcie_rp0 on end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
#TODO: TCP1 is used as USB Type-A
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
#TODO: TCP2 is used as HDMI
#TODO: TCP3 goes to redriver, then mux, then USB Type-C
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""TBT Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB Type-A""
register "type" = "UPC_TYPE_USB3_A"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref tcss_dma0 on end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port1 GEN2 */
[1] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port2 GEN1 */
[2] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TBT TYPEC USB2.0 */
[4] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TYPEC USB2.0 */
[6] = USB2_PORT_MID(OC_SKIP), /* Camera */
[9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* TODO: USB port1 GEN1 */
}"
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c5 on
# Smart Amplifier I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
chip drivers/i2c/tas5825m
register "id" = "0"
device i2c 4e on end # (8bit address: 0x9c)
end
end
device ref pcie_rp1 on
# PCH RP#1 x1, Clock 0 (CARD)
register "pcie_rp[PCH_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp2 on
# PCH RP#2 x1, Clock 2 (WLAN)
register "pcie_rp[PCH_RP(2)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp10 on
# PCH RP#10 x4, Clock 7 (SSD2)
# This uses signals PCIE_13 through PCIE_16 in the schematics
# but is identified as root port 10 in firmware.
register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp11 on
# CPU RP#11 x4, Clock 8 (SSD1)
# This uses signals PCIE_17 through PCIE_20 in the schematics
# but is identified as root port 11 in firmware.
register "pcie_rp[PCIE_RP(11)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
// TODO: Pin Mux settings
// Enable TCP1 and TCP3 USB-A conversion
// BIT 0:3 is mapping to PCH XHCI USB2 port
// BIT 4:5 is reserved
// BIT 6 is orientational
// BIT 7 is enable
//params->EnableTcssCovTypeA[1] = 0x81;
//params->EnableTcssCovTypeA[3] = 0x85;
// Disable reporting CPU C10 state over eSPI (causes LED flicker).
params->PchEspiHostC10ReportEnable = 0;
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
static size_t get_spd_index(void)
{
// BOARD_ID1 is high if 5600 MT/s and low if 4800 MT/s
if (gpio_get(GPP_E11)) {
return 1;
} else {
return 0;
}
}
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR5,
.ect = true,
.LpDdrDqDqsReTraining = 1,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_MIXED,
.cbfs_index = get_spd_index(),
.smbus[1] = { .addr_dimm[0] = 0x52, },
};
const bool half_populated = false;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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