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PCI subsystem: Drop PCI_64BIT_PREF_MEM option

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No board in the tree selects this and it looks like the implementation
was done at chipset level while it should be part of PCI subsystem.

When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test.

Feature of placing prefetchable PCI memory above 4GB may not work if
there is any 32-bit only prefetchable PCI BARs in the system.

Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2015-03-17 06:42:54 +02:00
parent 58e26c74e0
commit fcbebb61c5
22 changed files with 6 additions and 913 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/device/Kconfig
View File

@@ -205,11 +205,6 @@ config PCI
bool
default n
config PCI_64BIT_PREF_MEM
bool
depends on PCI
default n
config HYPERTRANSPORT_PLUGIN_SUPPORT
bool
depends on PCI

35
src/device/device.c
View File

@@ -611,19 +611,14 @@ static void allocate_resources(struct bus *bus, struct resource *bridge,
}
}
#if CONFIG_PCI_64BIT_PREF_MEM
#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#else
#define MEM_MASK (IORESOURCE_MEM)
#endif
#define IO_MASK (IORESOURCE_IO)
#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#define MEM_TYPE (IORESOURCE_MEM)
#define IO_TYPE (IORESOURCE_IO)
struct constraints {
struct resource pref, io, mem;
struct resource io, mem;
};
static void constrain_resources(struct device *dev, struct constraints* limits)
@@ -644,10 +639,8 @@ static void constrain_resources(struct device *dev, struct constraints* limits)
continue;
}
/* PREFETCH, MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == PREF_TYPE)
lim = &limits->pref;
else if ((res->flags & MEM_MASK) == MEM_TYPE)
/* MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == MEM_TYPE)
lim = &limits->mem;
else if ((res->flags & IO_MASK) == IO_TYPE)
lim = &limits->io;
@@ -696,8 +689,6 @@ static void avoid_fixed_resources(struct device *dev)
printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
/* Initialize constraints to maximum size. */
limits.pref.base = 0;
limits.pref.limit = 0xffffffffffffffffULL;
limits.io.base = 0;
limits.io.limit = 0xffffffffffffffffULL;
limits.mem.base = 0;
@@ -709,9 +700,7 @@ static void avoid_fixed_resources(struct device *dev)
continue;
printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__,
dev_path(dev), res->index, res->limit);
if ((res->flags & MEM_MASK) == PREF_TYPE &&
(res->limit < limits.pref.limit))
limits.pref.limit = res->limit;
if ((res->flags & MEM_MASK) == MEM_TYPE &&
(res->limit < limits.mem.limit))
limits.mem.limit = res->limit;
@@ -730,10 +719,8 @@ static void avoid_fixed_resources(struct device *dev)
if ((res->flags & IORESOURCE_FIXED))
continue;
/* PREFETCH, MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == PREF_TYPE)
lim = &limits.pref;
else if ((res->flags & MEM_MASK) == MEM_TYPE)
/* MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == MEM_TYPE)
lim = &limits.mem;
else if ((res->flags & IO_MASK) == IO_TYPE)
lim = &limits.io;
@@ -1045,11 +1032,6 @@ void dev_configure(void)
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)
continue;
if (res->flags & IORESOURCE_PREFETCH) {
compute_resources(child->link_list,
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
compute_resources(child->link_list,
res, MEM_MASK, MEM_TYPE);
@@ -1077,11 +1059,6 @@ void dev_configure(void)
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)
continue;
if (res->flags & IORESOURCE_PREFETCH) {
allocate_resources(child->link_list,
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
allocate_resources(child->link_list,
res, MEM_MASK, MEM_TYPE);

4
src/mainboard/asus/kfsn4-dre/Kconfig
View File

@@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 12

4
src/mainboard/asus/m2n-e/Kconfig
View File

@@ -62,10 +62,6 @@ config MAINBOARD_PART_NUMBER
string
default "M2N-E"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 2

4
src/mainboard/gigabyte/ga_2761gxdk/Kconfig
View File

@@ -42,10 +42,6 @@ config MAINBOARD_PART_NUMBER
string
default "GA-2761GXDK"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 2

4
src/mainboard/gigabyte/m57sli/Kconfig
View File

@@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER
string
default "GA-M57SLI-S4"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 2

4
src/mainboard/msi/ms7260/Kconfig
View File

@@ -44,10 +44,6 @@ config MAINBOARD_PART_NUMBER
string
default "MS-7260"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 2

4
src/mainboard/msi/ms9282/Kconfig
View File

@@ -37,10 +37,6 @@ config MAINBOARD_PART_NUMBER
string
default "MS-9282"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 4

4
src/mainboard/nvidia/l1_2pvv/Kconfig
View File

@@ -48,10 +48,6 @@ config MAINBOARD_PART_NUMBER
string
default "l1_2pvv"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 4

4
src/mainboard/tyan/s2912/Kconfig
View File

@@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER
string
default "S2912"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 4

4
src/mainboard/tyan/s2912_fam10/Kconfig
View File

@@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
string
default "S2912 (Fam10)"
config PCI_64BIT_PREF_MEM
bool
default n
config MAX_CPUS
int
default 12

77
src/northbridge/amd/agesa/family10/northbridge.c
View File

@@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void amdfam10_domain_enable_resources(device_t dev)
@@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
static void amdfam10_domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);

79
src/northbridge/amd/agesa/family12/northbridge.c
View File

@@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
//- pci_domain_read_resources(dev);
struct resource *resource;
/* Initialize the system-wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev)
resource->limit = 0xdfffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
#else
struct bus *link;
struct resource *resource;
for(link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}
@@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for(link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for(res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);

82
src/northbridge/amd/agesa/family14/northbridge.c
View File

@@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link = dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0 | (link->link_num << 2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1 | (link->link_num << 2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2 | (link->link_num << 2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void setup_uma_memory(void)
@@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1 | (link->link_num << 2));
mem2 = find_resource(dev, 2 | (link->link_num << 2));
printk(BIOS_DEBUG,
"base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
(u32) (mem1->base), (u32) (mem1->limit),
(u32) (mem1->size), u32) (mem1->align));
printk(BIOS_DEBUG,
"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
(u32) (mem2->base), (u32) (mem2->limit),
(u32) (mem2->size), (u32) (mem2->align));
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff))
|| ((mem1->limit > 0xffffffff)
&& (mem2->limit > 0xffffffff))) {
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
} else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG,
"base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG,
"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next) {
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);

77
src/northbridge/amd/agesa/family15/northbridge.c
View File

@@ -658,30 +658,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void domain_enable_resources(device_t dev)
@@ -782,10 +759,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -796,56 +769,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);

77
src/northbridge/amd/agesa/family15rl/northbridge.c
View File

@@ -652,30 +652,7 @@ static void domain_read_resources(struct device *dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void domain_enable_resources(struct device *dev)
@@ -776,10 +753,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(struct device *dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -790,56 +763,6 @@ static void domain_set_resources(struct device *dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);

77
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@@ -651,30 +651,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void domain_enable_resources(device_t dev)
@@ -775,10 +752,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -789,56 +762,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);

77
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@@ -666,30 +666,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void domain_enable_resources(device_t dev)
@@ -792,10 +769,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);

76
src/northbridge/amd/amdfam10/northbridge.c
View File

@@ -611,29 +611,8 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for(link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
#if CONFIG_MMCONF_SUPPORT
struct resource *res = new_resource(dev, 0xc0010058);
res->base = CONFIG_MMCONF_BASE_ADDRESS;
@@ -729,10 +708,6 @@ static void setup_uma_memory(void)
static void amdfam10_domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
int i, idx;
@@ -742,57 +717,6 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for(link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for(res = dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm);

68
src/northbridge/amd/amdk8/northbridge.c
View File

@@ -634,13 +634,6 @@ static void amdk8_domain_read_resources(device_t dev)
}
pci_domain_read_resources(dev);
#if CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
#endif
}
static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
@@ -871,10 +864,6 @@ static void setup_uma_memory(void)
static void amdk8_domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -884,63 +873,6 @@ static void amdk8_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if 0
/* Place the IO devices somewhere safe */
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1);
mem2 = find_resource(dev, 2);
#if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first
*/
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
#if 1
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
for(res = dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = my_find_pci_tolm(dev->link_list);
// FIXME handle interleaved nodes. If you fix this here, please fix

75
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@@ -643,29 +643,8 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM))
pci_domain_read_resources(dev);
else {
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
}
}
static void domain_enable_resources(device_t dev)
@@ -769,10 +748,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -783,56 +758,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);

78
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@@ -652,31 +652,7 @@ static void domain_read_resources(device_t dev)
}
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
struct resource *resource;
for (link=dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
}
#endif
}
static void domain_enable_resources(device_t dev)
@@ -785,10 +761,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -799,56 +771,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
mem1 = find_resource(dev, 1|(link->link_num<<2));
mem2 = find_resource(dev, 2|(link->link_num<<2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
/* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
{
/* If so place the one with the most stringent alignment first */
if (mem2->align > mem1->align) {
struct resource *tmp;
tmp = mem1;
mem1 = mem2;
mem2 = tmp;
}
/* Now place the memory as high up as it will go */
mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1);
}
else {
/* Place the resources as high up as they will go */
mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1);
}
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
}
for (res = &dev->resource_list; res; res = res->next)
{
res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
#endif
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);