- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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85
src/cpu/amd/mtrr/amd_mtrr.c
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85
src/cpu/amd/mtrr/amd_mtrr.c
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#include <console/console.h>
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#include <device/device.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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static unsigned long resk(uint64_t value)
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{
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unsigned long resultk;
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if (value < (1ULL << 42)) {
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resultk = value >> 10;
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}
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else {
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resultk = 0xffffffff;
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}
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return resultk;
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}
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void amd_setup_mtrrs(void)
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{
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unsigned long mmio_basek, tomk;
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unsigned long i;
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device_t dev;
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msr_t msr;
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x86_setup_mtrrs();
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/* Except for the PCI MMIO hole just before 4GB there are no
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* significant holes in the address space, so just account
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* for those two and move on.
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*/
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mmio_basek = tomk = 0;
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for(dev = all_devices; dev; dev = dev->next) {
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struct resource *res, *last;
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last = &dev->resource[dev->resources];
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for(res = &dev->resource[0]; res < last; res++) {
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unsigned long topk;
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if (!(res->flags & IORESOURCE_MEM) ||
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(!(res->flags & IORESOURCE_CACHEABLE))) {
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continue;
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}
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topk = resk(res->base + res->size);
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if (tomk < topk) {
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tomk = topk;
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}
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if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
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mmio_basek = topk;
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}
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}
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}
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if (mmio_basek > tomk) {
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mmio_basek = tomk;
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}
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/* Round mmio_basek down to the nearst size that will fit in TOP_MEM */
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mmio_basek = mmio_basek & ~TOP_MEM_MASK_KB;
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/* Round tomk up to the next greater size that will fit in TOP_MEM */
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tomk = (tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
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disable_cache();
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/* Setup TOP_MEM */
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msr.hi = mmio_basek >> 22;
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msr.lo = mmio_basek << 10;
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wrmsr(TOP_MEM, msr);
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/* Setup TOP_MEM2 */
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msr.hi = tomk >> 22;
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msr.lo = tomk << 10;
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wrmsr(TOP_MEM2, msr);
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/* zero the IORR's before we enable to prevent
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* undefined side effects.
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*/
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msr.lo = msr.hi = 0;
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for(i = IORR_FIRST; i <= IORR_LAST; i++) {
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wrmsr(i, msr);
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}
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
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wrmsr(SYSCFG_MSR, msr);
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enable_cache();
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}
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